參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 19 of 92
MASTER CLOCK AND PLL
Using the Oscillator
The ADAU1445/ADAU1446 can use an on-board oscillator to
generate its master clock. However, an external crystal must be
attached to complete the oscillator circuit. The on-board oscillator
is designed to work with a 256 × fS,NORMAL master clock, which is
12.288 MHz when fS,NORMAL is 48 kHz and 11.2896 MHz when
fS,NORMAL is 44.1 kHz. The resonant frequency of this crystal should
be in this range even in the case when the core is processing
dual- or quad-rate signals. When the core is processing dual-
rate signals (for example, fS,DUAL = 88.2 kHz or 96 kHz), resonant
frequency of the crystal should be 128 × fS,DUAL; when the core is
processing quad-rate signals (for example, fS,QUAD = 192 kHz),
the resonant frequency of the crystal should be 64 × fS,QUAD.
The external crystal in the circuit should be an AT-cut parallel
resonance device operating at its fundamental frequency.
Ceramic resonators should not be used. Figure 9 shows the
crystal oscillator circuit recommended for proper operation.
C1
100
XTALO
C2
XTALI
07
69
6-
0
09
Figure 9. Crystal Oscillator Circuit
The 100 Ω damping resistor on XTALO provides the oscillator
with a voltage swing of approximately 2.2 V at the XTALI pin.
The crystal shunt capacitance should be 7 pF. Its optimal load
capacitance, specified by the manufacturer, should be about 18 pF,
although the circuit supports values up to 25 pF. The equivalent
series resistance should also be as small as possible. The necessary
values of Load Capacitor C1 and Load Capacitor C2 can be
calculated from the crystal load capacitance with the following
equation:
STRAY
2
1
2
1
L
C
+
×
=
where CSTRAY is the stray capacitance in the circuit and is usually
assumed to be approximately 2 pF to 5 pF.
Short trace lengths in the oscillator circuit decrease stray
capacitance, thereby increasing the loop gain of the circuit and
helping to avoid crystal start-up problems.
On the ADAU1445/ADAU1446 evaluation boards, the capac-
itance value for C1 and C2 is 22 pF.
XTALO should not be used to directly drive the crystal signal to
another IC. This signal is an analog sine wave and is not appro-
priate to drive a digital input. A separate pin, CLKOUT, is provided
for this purpose. CLKOUT can output 256 × fS,NORMAL, 512 ×
fS,NORMAL, or a buffered, digital copy of the crystal oscillator
signal to other ICs in the system. CLKOUT is set up using the
CLKMODEx pins. For a more detailed explanation of CLKOUT,
section.
Setting Master Clock and PLL Mode
The ADAU1445/ADAU1446 master clock input feeds a PLL, which
generates the 3584 × fS,NORMAL clock (172.032 MHz when fS,NORMAL
is 48 kHz) to run the DSP core. This rate is referred to as fCORE.
In normal operation, the input to the master clock must be one
of the following: 64 × fS,NORMAL, 128 × fS,NORMAL, 256 × fS,NORMAL,
384 × fS,NORMAL, or 512 × fS,NORMAL, where fS,NORMAL is the audio
sampling rate with the core in normal-rate processing mode.
The PLL divider mode is set by PLL0, PLL1, and PLL2 as
detailed in Table 7.
If the ADAU1445/ADAU1446 cores are set to receive dual-rate
signals (by reducing the number of program steps per sample by
a factor of 2 using the DSP core rate select register), then the master
clock frequency must be 32 × fS,DUAL, 64 × fS,DUAL, 128 × fS,DUAL,
192 × fS,DUAL, or 256 × fS,DUAL.
If the ADAU1445/ADAU1446 cores are set to receive quad-rate
signals (by reducing the number of program steps per sample by
a factor of 4 using the DSP core rate select register), then the master
clock frequency must be 16 × fS,QUAD, 32 × fS,QUAD, 64 × fS,QUAD,
96 × fS,QUAD, or 128 × fS,QUAD. On power-up, a clock signal must
be present on XTALI so that the ADAU1445/ADAU1446 can
complete its initialization routine.
If, at any point during operation, the clock signal is removed
from XTALI, the DSP should be reset to avoid unpredictable
behavior on output pins. The clock mode should not be changed
without also resetting the ADAU1445/ADAU1446. If the mode
is changed during operation, a click or pop can result on the
outputs. The state of the PLLx pins should be changed while
RESET is held low.
The phase-locked loop uses the PLL mode select pins (PLL0,
PLL1, and PLL2) to derive a 64 × fS,NORMAL clock from whatever
signal is present at the XTALI pin. This clock signal is multiplied
by 56 to produce the core clock. Therefore, fCORE is 3584 × fS,NORMAL.
In a system with a fS,NORMAL of 48 kHz, the PLL derives a 3.072 MHz
clock and then multiplies it by 56 to produce a 172.032 MHz
core clock.
The core clock (fCORE) should never exceed 172.032 MHz,
though it may be lower in some applications.
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