參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 21 of 92
PLL Loop Filter
The PLL loop filter should be connected to the PLL_FILT pin. This
filter, shown in Figure 11, includes three passive components—
two capacitors and a resistor. The values of these components
do not need to be exact; the tolerance can be up to 10% for the
resistor and up to 20% for each capacitor. The 3.3 V signal shown
in the schematic can be connected to the PVDD supply of the chip.
ADAU1445/
ADAU1446
1.5k
PLL_FILT
33nF
1.8nF
PVDD
07
69
6-
0
11
Figure 11. PLL Loop Filter
Using the ADAU1445/ADAU1446 as Clock Masters
To output a master clock from the ADAU1445/ADAU1446 to
other chips in the system, the CLKOUT pin is used. To set the
frequency of this clock signal, the CLKMODEx pins must be set
(see Table 8).
Table 8. CLKOUT Modes
CLKOUT Signal
CLKMODE1
CLKMODE0
Disabled
0
Buffered Oscillator
0
1
256 × fS,NORMAL
1
0
512 × fS,NORMAL
1
Master Clock and PLL Modes and Settings
DSP Core Rate Select Register (Address 0xE220)
The core’s start pulse initiates the operation of the core and
determines the sample rate of signals processed inside the core.
This pulse can originate from one of three internally generated
fS signals (fS,NORMAL, fS,DUAL, or fS,QUAD), one of the 12 serial input fS
signals (an LRCLK signal associated with a serial input port),
one of the 12 serial output fS signals (an LRCLK signal associated
with a serial output port), or LRCLK recovered from the S/PDIF
receiver input.
Setting the value of the DSP core rate select register sets the speed
of the DSP core (see Table 10). By default, the signals processed
in the core are at the normal DSP core rate; therefore, the core
clock is 3584 × fS, NORMAL. For a system processing signals in the
core at the dual rate, the start pulse should be set to the internally
generated dual rate, and the core clock is 1792 × fS,DUAL. For a
system processing signals in the core at the quad rate, the start
pulse should be set to the internally generated quad rate, and
the core clock is 896 × fS,QUAD.
Master Clock Enable Switch Register (Address 0xE280)
For power-saving purposes, various parts of the chip can be
switched on and off. Setting the appropriate bit to 0 disables the
corresponding subsystem, and setting the bit to 1 enables the
subsystem. This is the first register that should be set after the
device is powered on and completes its initialization. Failure to
set this register may compromise future register writes.
Table 9. Bit Descriptions of Register 0xE280
Bit Position
Description1
Default
[15:9]
Reserved
[8]
Enable MCLK to auxiliary ADCs
0
[7]
Enable MCLK to S/PDIF transmitter
0
[6]
Enable MCLK to S/PDIF receiver
0
[5]
Enable MCLK to DSP core
0
[4]
Enable MCLK to Stereo ASRC[7:4]2
0
[3]
Enable MCLK to Stereo ASRC[3:0]2
0
[2]
Enable MCLK to serial outputs
0
[1]
Enable MCLK to serial inputs
0
[0]
Enable MCLK to flexible audio routing
matrix (FARM)
0
1 0 = disable, 1 = enable.
2 See the Flexible Audio Routing Matrix—Input Side section for more
information.
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