參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 37/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 42 of 92
Table 28. Bit Descriptions of Serial Output Port Modes Registers
Bit Position
Description
Default
[15]
Clock output enable1
0
0 = LRCLK and BCLK output pins disabled
1 = LRCLK and BCLK output pins enabled
[14]
Frame sync type
0
0 = LRCLK 50/50 duty cycle clock signal (square wave)
1 = LRCLK synchronization pulse (narrow pulse)
[13:10]
Clock domain master/slave select1
Address specific2
0000 = slave to Clock Domain 3 (Port 1)
0001 = slave to Clock Domain 4 (Port 2)
0010 = slave to Clock Domain 5 (Port 3)
0011 = slave to Clock Domain 6 (Port 4)
0100 = slave to Clock Domain 7 (Port 5)
0101 = slave to Clock Domain 8 (Port 6)
0110 = slave to Clock Domain 9 (Port 7)
0111 = slave to Clock Domain 10 (Port 8)
1000 = slave to Clock Domain 11 (Port 9)
1001 = master, clock is fS,NORMAL
1010 = master, clock is fS,DUAL
1011 = master, clock is fS,QUAD
[9]
Serial output BCLK polarity
0
0 = negative BCLK polarity
1 = positive BCLK polarity
[8]
Serial output LRCLK polarity
0
0 = negative BCLK polarity
1 = positive BCLK polarity
[7:6]
Word length
00
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = flexible TDM mode3
[5:3]
MSB position
000
000 = I2S (delayed by 1)
001 = left justified (delayed by 0)
010 = delayed by 8
011 = delayed by 12
100 = delayed by 16
[2:0]
TDM type
000
000 = TDM2 (stereo)
001 = TDM4
010 = TDM8 or flexible TDM mode3
011 = TDM16
100 = packed TDM4
1 Bit 15 and Bits[13:10] must be used in conjunction to set the port as a master or slave.
2 The default depends on the address: 0x040 = 0000, 0xE041 = 0001, 0xE042 = 0010, 0xE043 = 0011, 0xE044 = 0100, 0xE045 = 0101, 0xE046 = 0110, 0xE047 = 0111,
0xE048 = 1000, and 0xE049 = 1001.
3 To activate flexible TDM mode, both Bits[7:6] and Bits[2:0] must be set.
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