參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 44 of 92
FLEXIBLE AUDIO ROUTING MATRIX (FARM)
The routing matrix distributes audio signals among the serial
inputs, serial outputs, ASRCs, S/PDIF receiver and transmitter,
and DSP core. This simplifies the design of complex systems
that require many inputs and outputs with different sample
rates. It also allows signals to be routed in hardware, instead of
in software.
Routing Matrix Block Diagram
Figure 36 shows an overview of audio routing in the ADAU1445/
ADAU1446 and details the interaction among the S/PDIF I/O,
serial I/O, ASRCs, and DSP via the routing matrix. To reduce
the complexity of the system, audio signals are routed in pairs.
Therefore, in Figure 36, each solid line represents a stereo pair
of audio signals. The corresponding channel numbers are
written above the lines. The dotted lines at the bottom of the
diagram represent clock signals. The two large gray boxes represent
the flexible audio routing matrix, in which one-to-one connections
can be made between any input and any output. The signal routing
is fully implemented in hardware.
System Delay
Routing data through the serial ports, routing matrix, ASRCs,
and DSP core results in a brief delay between the time when an
audio sample is input to the IC and when it is output. If the DSP
is programmed to simply pass serial inputs to serial outputs with
no sample rate conversion or additional processing, the minimum
observed delay of an audio sample from the SDATA_INx pin to
the SDATA_OUTx pin is equal to four sample periods. At a sample
rate of 48 kHz, this corresponds to 83 μs. The system delay increases
as sample rate conversion or additional processing is implemented
in the system.
SERIAL
INPUT
PORTS
(×9)
INPUT
CHANNELS
(24 CH)
F
L
E
X
IBL
E
A
UDI
O
RO
UT
IN
G
M
AT
R
IX
IN
PUT
SI
D
E
F
L
E
X
IBL
E
A
UDI
O
RO
UT
IN
G
M
AT
R
IX
OU
T
P
U
T
S
ID
E
OUTPUT
CHANNELS
(24 CH)
SERIAL
OUTPUT
PORTS
(×9)
STEREO
ASRCS
(8 × 2 CH)
S/PDIF Tx
ASRC I/O
(16 CH)
SERIAL I/O
(24 CH)
RATE
SERIAL
INPUT
MODES
CLOCK DOMAINS (×12)
0 TO 2
3 TO 8
9 TO 11
S/PDIF Rx
S/PDIF I/O
(2 CH)
DSP CORE
MASTER/SLAVE
SELECT
AUT
O
M
AT
IC
I
N
PUT
CHANNEL
ASSI
G
N
M
E
NT
A
UT
O
M
AT
IC
O
UT
P
U
T
CHA
NNE
L
A
S
IG
NM
E
NT
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
8
BCL
K0
/L
RCL
K0
BCL
K1
/L
RCL
K1
BCL
K2
/L
RCL
K2
BCL
K3
/L
RCL
K3
BCL
K4
/L
RCL
K4
BCL
K5
/L
RCL
K5
BCL
K6
/L
RCL
K6
BCL
K7
/L
RCL
K7
BCL
K8
/L
RCL
K8
BCL
K9
/L
RCL
K9
BCL
K1
0
/L
RCL
K1
0
BCL
K1
1
/L
RCL
K1
1
P
S
L
2
12
6
2
222
2
SPDIFI
SPDIFO
S/PDIF OUTPUT
ON MP PINS
IN
F
R
O
M
A
S
R
C
S
O
U
T
TO
AS
R
C
S
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
SERIAL
OUTPUT
MODES
07
69
6-
03
7
Figure 36. Routing Matrix Block Diagram
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