參數(shù)資料
型號： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 2/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 10 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LRCLK2
SDATA_IN1
BCLK1
LRCLK1
SDATA_IN0
BCLK0
DGND
IOVDD
LRCLK0
MP11
MP10
MP9
MP8
ADDR0
CLATCH
SCL/CCLK
SDA/COUT
ADDR1/CDATA
DVDD
DGND
IOVDD
BCLK3
LRCLK3
SDATA_IN2
BCLK2
SDATA_OUT6
LRCLK10
BCLK10
SDATA_OUT7
LRCLK11
BCLK11
IOVDD
DGND
SDATA_OUT8
PLL0
PLL1
MP0/ADC0
NOTES
1. THE EXPOSED PAD DOES NOT HAVE AN INTERNAL ELECTRICAL CONNECTION TO THE INTEGRATED CIRCUIT,
BUT SHOULD BE CONNECTED TO THE GROUND PLANE OF THE PCB FOR PROPER HEAT DISSIPATION.
MP1/ADC1
MP2/ADC2
MP3/ADC3
CLKOUT
IOVDD
DGND
DVDD
BCLK8
SDATA_IN8
SDATA_OUT5
LRCLK9
BCLK9
DV
DD
S
D
AT
A_I
N
3
S
D
AT
A_O
U
T
0
L
RCL
K
4
BCL
K4
S
D
AT
A_I
N
4
S
D
AT
A_O
U
T
1
L
RCL
K
5
BCL
K5
S
D
AT
A_I
N
5
S
D
AT
A_O
U
T
2
IOV
D
DG
ND
DV
DD
L
RCL
K
6
BCL
K6
S
D
AT
A_I
N
6
S
D
AT
A_O
U
T
3
L
RCL
K
7
BCL
K7
S
D
AT
A_I
N
7
S
D
AT
A_O
U
T
4
L
RCL
K
8
IOV
D
DG
ND
DG
ND
IOV
D
SEL
F
B
O
T
CL
KM
O
DE
1
CL
KM
O
DE
0
RS
V
D
PL
L
2
MP
7
MP
6
MP
5
MP
4
DV
DD
DG
ND
IOV
D
V
DRI
V
E
XT
A
L
O
XT
A
L
I
P
L
L_
FI
L
T
PV
D
PG
N
D
SP
D
IF
I
SP
D
IF
O
AV
D
AG
ND
DV
DD
RESET
PIN 1
ADAU1445/ADAU1446
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41
42 43 44 45 46 47
48 49 50
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
07
69
6-
0
07
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 13, 26,
38, 51,
62, 76,
88
DGND
PWR
Digital Ground. The AGND, DGND, and PGND pins should be tied directly together in a common
ground plane. DGND pins should be decoupled to a DVDD pin with a 100 nF capacitor.
2, 14, 27,
39, 52,
63, 77,
89
IOVDD
PWR
Input and Output Supply. The voltage on this pin sets the highest input voltage that should be
present on the digital input pins. This pin is also the supply for the digital output signals on the
clock, data, control port, and MP pins. IOVDD should always be set to 3.3 V. The current draw of this
pin is variable because it is dependent on the loads of the digital outputs.
3
BCLK3
D_IO
Bit Clock, Input/Output Clock Domain 3. This pin is bidirectional, with the direction depending on
whether the Input/Output Clock Domain 3 is set up as a master or slave. When not used, this pin
can be left disconnected.
4
LRCLK3
D_IO
Frame Clock, Input/Output Clock Domain 3. This pin is bidirectional, with the direction depending on
whether the Input/Output Clock Domain 3 is set up as a master or slave. When not used, this pin
can be left disconnected.
5
SDATA_IN2
D_IN
Serial Data Port 2 Input. When not used, this pin can be left disconnected.
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