參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/92頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 33 of 92
Serial Clock Modes and Settings
Dejitter Window Register (Address 0xE221)
Table 19. Bit Descriptions of Register 0xE221
Bit
Position
Description
Default
[15:6]
Reserved
[5:0]
Dejitter window
001000
000000 = dejitter circuit bypass
000001 = minimum window
…
111111 = maximum window
Register 0xE221 is a single 6-bit register that sets the size of the
dejitter window. The dejitter circuit prevents samples from being
repeated or omitted altogether due to jitter in the frame clock
pulses coming from the serial ports in slave mode.
The dejitter window is set by default to 8 MCLK samples, which
should be suitable for most applications. However, Register 0xE221
allows this value to be tweaked in case of problems, or it allows
the dejitter circuit to be bypassed altogether by setting Bits[5:0]
to 000000.
Clock Pad Multiplexer Register (Address 0xE240)
Table 20. Bit Descriptions of Register 0xE240
Bit Position
Clock Domain1
Default
[15:6]
Reserved
[5]
Clock Domain 8
0
[4]
Clock Domain 7
0
[3]
Clock Domain 6
0
[2]
Clock Domain 5
0
[1]
Clock Domain 4
0
[0]
Clock Domain 3
0
1 0 = input clock domain, 1 = output clock domain.
There are six clock domains (Clock Domains[8:3]) that can be
either input or output clock domains. This is determined by a
single bit for each clock domain (see Table 20), where a setting
of 0 corresponds with an input clock domain and a setting of 1
corresponds with an output clock domain.
In Figure 28, the clock pad multiplexer is represented by six 4:2
multiplexers.
ASSIGNABLE
INPUT/OUTPUT
CLOCK DOMAINS
(×6)
3TO 8
BC
L
K
3
/L
R
C
L
K3
BC
L
K
4/
L
RCL
K
4
BC
L
K
5
/L
R
C
L
K5
BC
L
K
6/
L
RCL
K
6
BC
L
K
7/
L
RCL
K
7
BC
L
K
8/
L
RCL
K
8
2
4:2
CLOCK PAD
MULTIPLEXERS
TO SERIAL INPUT PORTS
TO SERIAL OUTPUT PORTS
2
0
76
96
-0
27
Figure 28. Clock Pad Multiplexer
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