參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 43/92頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 48 of 92
Sample Rate Conversion Before the DSP
If asynchronous input signals are present in the system, they
must be routed through the ASRC before being processed by
the DSP. This is made possible by routing the asynchronous
signals through the input side of the routing matrix to the
ASRC inputs. This is illustrated in Figure 43.
In such a situation, the ASRC target sample rate should be set
synchronous to the DSP. After conversion, the signals are
passed to the DSP and are then available in SigmaStudio in the
ASRC input cell.
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
FROM SERIAL
INPUT PORTS
FROM
S/PDIF Rx
STEREO
ASRCs
(8 × 2 CH)
RATE
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
8
TO DSP
07
69
6-
04
4
FARM
Figure 43. Routing Asynchronous Input Signals to DSP Inputs
Sample Rate Conversion After the DSP
After processing signals in the DSP, it is sometimes desirable to
output them asynchronous to the DSP rate, for example, when
an asynchronous external DAC is in the system. This can be
accomplished by routing the signals through the input side of
the routing matrix from the DSP-to-ASRC pairs to the ASRC
inputs. This is illustrated in Figure 44.
In this situation, the ASRC target sample rate can be set to any
desired value, and the audio data is sent to the output side of the
routing matrix.
TO FARM
(OUTPUT SIDE)
FROM DSP
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
FROM SERIAL
INPUT PORTS
STEREO
ASRCs
(8 × 2 CH)
RATE
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
8
0
7696
-0
45
FARM
Figure 44. Routing DSP Outputs to Asynchronous Output Signals
DSP Inputs and Outputs
In the DSP, the signals are represented as input and output blocks
within the SigmaStudio development tool and then undergo
processing as determined by the SigmaStudio schematic. There
are 21 input and output channel pairs, as shown in Figure 45. In
SigmaStudio, each pair is accessible as individual channels and,
therefore, does not need to remain as a pair.
FROM
INPUT
CHANNELS
TO FARM
(OUTPUT SIDE)
S/PDIF Tx
S/PDIF Rx
SPDIFI
SPDIFO
ASRC I/O
(16 CH)
SERIAL I/O
(24 CH)
S/PDIF I/O
(2 CH)
DSP CORE
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
IN
F
R
O
M
AS
RCs
O
UT
T
O
AS
RCs
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
07
69
6-
0
46
Figure 45. DSP Core Input and Output Signals
Some algorithms running inside the SigmaStudio signal flow
may mix or split channels within the DSP. Therefore, the
number of output pairs does not necessarily have to equal the
number of input pairs.
Note that, while the S/PDIF Rx pair can be routed either to the
FARM input side or directly to the DSP, the S/PDIF Tx pair
must be routed directly to the S/PDIF output pin (SPDIFO),
bypassing the FARM output side.
The ASRC I/O block in Figure 45 represents the interaction
between the DSP and the ASRCs. Inputs to the DSP from the
ASRCs (ASRC-to-DSP pairs) are represented in SigmaStudio as
ASRC input cells, whereas outputs to the ASRCs from the DSP
(DSP-to-ASRC pairs) are represented in SigmaStudio as ASRC
output cells. The cells are shown in their respective locations in
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
ASRC I/O
(16 CH)
IN
F
RO
M
AS
RC
s
OU
T
TO
A
S
R
C
s
07
69
6-
0
47
Figure 46. ASRC Input and Output Cells
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