Enable S/PDIF to I2S Output Register (Address " />
參數(shù)資料
型號(hào)： EVAL-ADAU1446EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 63/92頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADAU1446
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1446
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 板，軟件
ADAU1445/ADAU1446
Rev. A | Page 66 of 92
Enable S/PDIF to I2S Output Register (Address 0xE241)
This MP output is controlled by setting three bits in
Register 0xE241:
Table 62. Bit Descriptions of Register 0xE241
Bit Position
Description
Default
[15:3]
Reserved
[2]
Output mode
0
0 = I2S
1 = TDM
[1]
Group 2 enable
0
0 = Group 2 off
1 = Group 2 on
[0]
Group 1 enable
0
0 = Group 1 off
1 = Group 1 on
Bit 0 switches Group 1 on and off.
Bit 1 switches Group 2 on and off.
Bit 2 switches between I2S and TDM modes.
When S/PDIF to I2S mode is active, the pins described in Table 51
are used.
When TDM mode is active, Slot 0 and Slot 4 contain the audio
data, and Slot 1 contains the streamed block start, channel status,
user data, and validity bits (see Table 63). The bits are streamed
in real time and are synchronized to the audio data. Only the
seven MSBs of Slot 1 are used, as shown in Table 63. The corre-
sponding TDM format is shown in more detail in Figure 54.
Table 63. Function of Decoded Bits in Figure 54
The S/PDIF receiver can be set to send the stereo audio stream
and the auxiliary S/PDIF bits in I2S or TDM format on eight of
the 12 MP pins. The eight outputs are divided into two groups:
Group 1 converts S/PDIF to I2S (LRCLK, BCLK, and SDATA
signals), and Group 2 decodes the channel status and user data
bits (virtual LRCLK, user data, channel status, validity bit, and
block start signal).
Bit Position
Description
[31]
Block start (high for first 16 samples)
[30]
Channel status of right channel
[29]
Channel status of left channel
[28]
User data bit, right channel
[27]
User data bit, left channel
[26]
Validity bit, right channel
[25]
Validity bit, left channel
[24:0]
Not used
FRAME
LRCLKx
0123
4567
LEFT AUDIO
RIGHT AUDIO
DECODE BITS
01
24 BITS: LEFT AUDIO
7 DECODED
BITS
4
24 BITS: RIGHT AUDIO
07
69
6-
0
5
Figure 54. S/PDIF TDM Signal
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