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參數(shù)資料
| 型號(hào)： | CL-PS7500FE |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | System-on-a Chip for Internet Appliance |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 76/251頁 |
| 文件大?。?/td> | 2367K |
| 代理商： | CL-PS7500FE |
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June 1997
75
ADVANCE DATA BOOK v2.0
MEMORY SUBSYSTEMS
CL-PS7500FE
System-on-a-Chip for Internet Appliance
For normal operation, the VIDINITB register should be programmed to 0x00000000, so that the value in
the VIDCURB register is defined. All video channel registers should be programmed with addresses that
are qword aligned (that is, bits 3:0 are ‘0’).
There is an extra bit (30) in the VIDINITA register that must be programmed high if the address in the
VIDINITA register is the same as the address in the VIDEND register. At all other times it should be pro-
grammed low.
Once all bits have been programmed, the enable bit in the VIDCR can be written to, and the video DMA
channel becomes operational. The channel is then controlled by a video request signal from the video
controller part of CL-PS7500FE. When a request for more video data arrives and the current bus cycle
finishes, the bus controller arbitrates in favor of the DMA (having the highest priority on the bus) to fetch
a qword of data for the video sub system. Immediately after each DMA access, the address in the current
register is incremented by 16 (one qword) and the address is compared with the address in the VIDEND
register. If they are the same, the DMA controller knows that the next DMA is the last one in the buffer,
and after the next DMA, the current register is reloaded from the VIDSTART register. During the FLYBACK
period, the current register is automatically reloaded with the value in the VIDINITA register.
Programming of the DMA and video subsystem for use with dual panel LCDs is described in full in
Appendix B, “Dual-Panel Liquid Crystal Displays”
, and uses identical principles, except there are two Cur-
rent registers and two Init registers – one for each panel. On each successive DMA access, the
CL-PS7500FE toggles between the two sets of registers providing data first for the upper panel and then
from the lower panel. This means that the two init registers should always be programmed with addresses
with are equidistantly spaced through the wrapped-around frame buffer.
9.3.2
Cursor DMA
There are only two registers associated with the cursor channel, the CURSCUR current register and the
CURSINIT register. The channel is enabled under the control of the video enable bit in the VIDCR. The
operation of the channel is the same for normal or duplex modes, but it is necessary to program the cursor
differently depending on the mode being used. Details of the programming required can be found in
Appendix B, “Dual-Panel Liquid Crystal Displays”
.
The CURSINIT register should be programmed with the address of the first word of cursor data in mem-
ory. There is no END register as the width of the cursor is predetermined (32 pixels) and the height of the
cursor is defined by programming the VCSR and VCER in the video subsystem. Each qword fetches
results in two rasters worth of cursor data being transferred (except in HiRes mode). At the end of each
fetch, the value in the CURSCUR is increased by 16, to address the start of the next qword. The value
programmed into the CURSINIT register must be qword-aligned.
9.3.3
Sound DMA
The Sound DMA channel provides data for the CL-PS7500FE sound interface. There are two sets of
pointer registers so that data transfers can be double buffered to ensure that DMA data is always available
even when the data in one buffer is exhausted. One set of registers can be reprogrammed while the others
are being used.
Sound DMA transfers are constrained to a single 4-Kbyte page, as only the lowest 12 bits of the DMA
address are incremented and compared to check for the end of the buffer. All sound DMA is qword and
must be from qword aligned addresses, so the lowest four bits of the registers are not used and should
be programmed to zero. Bit 30 of each of the END registers is the ‘last’ bit and must be programmed high
if the initial value in the current register is the same as the end register for that buffer (that is, for a single
transfer).
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