
ADVANCE DATA BOOK v2.0
June 1997
42
ARM PROCESSOR MMU
CL-PS7500FE
System-on-a-Chip for Internet Appliance
6.3.5
Section Descriptor
6.4
Translating Section References
Figure 6-6 on page 44
illustrates the complete Section translation sequence. Note that the access per-
missions contained in the Level One descriptor must be checked before the physical address is gener-
ated. The sequence for checking access permissions is described in
Section 6.10.4 on page 50
.
6.4.1
Level Two Descriptor
If the Level One fetch returns a Page Table descriptor, this provides the base address of the page table
to be used. The page table is then accessed as described in
Figure 6-7 on page 45
, and a Page Table
a
‘X’ indicates a don’t care state.
Bit
Description
3:2
(C, B)
Control the cache- and write-buffer-related functions as follows:
G
C – Cacheable:
data at this address is placed in the cache (if the cache is enabled).
G
B – Bufferable: data at this address is written through the write buffer (if enabled).
4
Write as ‘1’ for backward compatibility.
8:5
Specify one of the sixteen possible domains (held in the Domain Access Control register) that contain the pri-
mary access controls.
11:10
(AP)
Specify the access permissions for this section (see
Table 6-2
). The interpretation depends upon the setting of
the S and R bits (control register bits 8 and 9). Note that the Domain Access Control specifies the primary
access control; the AP bits only have an effect in Client mode. Refer to
Section 6.9
.
19:12
Always write as ‘0’.
31:20
Form the corresponding bits of the physical address for the 1-Mbyte section.
Table 6-2.
Interpreting Access Permission (AP) Bits
AP
S
R
Supervisor
Permissions
User
Permissions
Notes
00
0
0
No access
No access
Any access generates a permission fault.
00
1
0
Read only
No access
Supervisor read-only permitted.
00
0
1
Read only
Read only
Any write generates a permission fault.
00
1
1
Reserved
01
X
a
X
Read/write
No access
Access allowed only in Supervisor mode.
10
X
X
Read/write
Read only
Writes in User mode cause permission fault.
11
X
X
Read/write
Read/write
All access types permitted in both modes.
XX
1
1
Reserved