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參數(shù)資料
| 型號： | CL-PS7500FE |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | System-on-a Chip for Internet Appliance |
| 中文描述： | 32-BIT, RISC MICROCONTROLLER, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 139/251頁 |
| 文件大小： | 2367K |
| 代理商： | CL-PS7500FE |
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ADVANCE DATA BOOK v2.0
June 1997
138
VIDEO MACROCELL INTERFACE
CL-PS7500FE
System-on-a-Chip for Internet Appliance
15. VIDEO MACROCELL INTERFACE
15.1
Bus Interface
The video macrocell does not use the ARM address bus. The address for programming video and sound
registers (0x03400000 to 0x034FFFFF) is decoded elsewhere in CL-PS7500FE and the internal nPROG
signal is generated as a general register write strobe. The specific register to be programmed is selected
according to the state of the upper bits of the 32-bit input data bus.
All video and sound data is then obtained by DMA under the control of the nVIDRQ internal request signal.
This signals to the main CL-PS7500FE bus arbitration logic that a DMA request is pending, and the
request will be serviced at the first available opportunity. All DMA is qword, so four complete data words
will be read from memory and stored in the appropriate video, cursor, or sound FIFO for each DMA burst.
Note that video DMA may be read from memory in bursts of more than 4 words allowing almost continu-
ous DRAM page mode access to occur.
The system software should create a video frame buffer in DRAM memory, and program the DMA address
pointers to the start, end, and desired initial location within the buffer. All DMA pointer addresses should
be qword aligned. Once the display is enabled, the video registers should only be programmed during the
FLYBACK period to ensure flicker free updating of the screen. See
Chapter 10
for details of how to pro-
gram the DMA controller.
15.2
Setting the FIFO Preload Value
The video FIFO is a 32-entry, 32-bit-wide FIFO. Words of video data are clocked into the top of the FIFO
under control of the internal CL-PS7500FE signals, BUSCLK and nVIDAK. Words are clocked out of the
bottom of the FIFO as the video system displays the data, controlled by the pixel clock.
The FIFO is flushed during vertical flyback time, so before the start of the frame the FIFO is empty. At the
start of the frame a video request is made to the memory subsystem by asserting the internal
CL-PS7500FE signal, nVIDRQ. When a predetermined number of words have been loaded into the FIFO
the request is removed. As the data in the FIFO is displayed, further video requests are made to refill the
FIFO to the desired level.
The Control register (CONREG) includes a 3-bit field (CONREG[10:8]) to set the preload value of the
video FIFO. In this way the FIFO can be programmed to load 4, 8, 12, 16, 20, 24, or 28 words of data into
the FIFO at the start of a frame. After the start of a frame, the FIFO will request more data when the num-
ber of words it contains falls below the preloaded value.
The point where the FIFO requests more data to be loaded is dependent upon system considerations:
G
If the FIFO is reloaded too late, there is a danger that it will run out of data (underflow)
G
If the FIFO is reloaded too early, then there is a danger that the data will not fit into the FIFO (overflow)
In general, the higher the bandwidth of the screen, the more words required to preload into the FIFO. In
a low bandwidth screen mode, it is not always desirable to have a large preload value, as the bus traffic
has long bursts of data transferred at the start of the frame.
The optimum value to preload depends upon the screen mode in use (that is, the rate the data is read
from the FIFO), and both the latency of the memory controller and the rate that data is provided to the
CL-PS7500FE. It is generally prudent to program the minimum value possible to keep the bus traffic even.
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