
ADVANCE DATA BOOK v2.0
CL-PS7500FE
System-on-a-Chip for Internet Appliance
June 1997
10
TABLE OF CONTENTS
20. BUS INTERFACE................................................................................................................ 187
20.1
Bus Arbitration................................................................................................................................187
20.2
Bus Cycle Types.............................................................................................................................187
20.3
Video DMA Bandwidth....................................................................................................................188
20.4
Video DMA Latency........................................................................................................................188
21. CLOCKS, POWER SAVING, AND RESET........................................................................ 191
21.1
Clock Control..................................................................................................................................191
21.1.1
Video and Sound Subsystem Clocks..............................................................................191
21.1.2
I/O Clock Outputs ...........................................................................................................191
21.1.3
Synchronous/Asynchronous Mode for the ARM Processor............................................191
21.1.4
Clock Prescalars.............................................................................................................192
21.1.5
Clocking Schemes..........................................................................................................192
21.2
Power Management........................................................................................................................192
21.2.1
SUSPEND Mode ............................................................................................................193
21.2.2
STOP Mode....................................................................................................................194
21.3
Reset..............................................................................................................................................195
22. ELECTRICAL SPECIFICATIONS...................................................................................... 196
22.1
Absolute Maximum Ratings............................................................................................................196
22.2
DC Specifications...........................................................................................................................197
22.2.1
DC Specifications — Digital Values................................................................................197
22.3
Derating..........................................................................................................................................198
22.4
AC Parameters — List of Timing Figures .......................................................................................199
22.5
System Reset Timing .....................................................................................................................200
22.6
Memory Subsystems......................................................................................................................201
22.7
I/O Subsystems..............................................................................................................................209
22.8
System Timing (Clocks)..................................................................................................................222
23. PACKAGE........................................................................................................................... 225
23.1
240-Pin PQFP Package Example...................................................................................................225
24. ORDERING INFORMATION EXAMPLE............................................................................ 226