參數(shù)資料
型號(hào): 935270538118
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 59/93頁(yè)
文件大?。?/td> 2118K
代理商: 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
62 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 24 — read
Code (Hex): A4 — write
10.4.5
Hc
PInterruptEnable register (25H—Read, A5H—Write)
The bits 6:0 in this register are the same as those in the Hc
PInterrupt register. They
are used together with bit 0 of the HcHardwareConguration register to enable or
disable the bits in the Hc
PInterrupt register.
On power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
2
AllEOT
Interrupt
0 — no event
1 — implies that data transfer has been completed via PIO transfer
or DMA transfer. Occurrence of internal or external EOT will set
this bit.
1
ATLInt
0 — no event
1 — implies that the microprocessor must read ATL data from
the HC. This requires that the HcBufferStatus register must rst be
read. The time for this interrupt depends on the number of clocks
bit set for USB activities in each ms.
0
SOFITLInt
0 — no event
1 — implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status,
the HcBufferStatus register must rst be read. This is for
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph in Section 9.5.
Table 43:
Hc
PInterrupt register: bit description…continued
Bit
Symbol
Description
Table 44:
Hc
PInterruptEnable register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ClkReady
HC
Suspended
Enable
OPR
Interrupt
Enable
reserved
EOT
Interrupt
Enable
ATL
Interrupt
Enable
SOF
Interrupt
Enable
Reset
00000000
Access
R/W
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