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參數(shù)資料
| 型號(hào)： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 21/93頁(yè) |
| 文件大小： | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
28 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
However, if communication with a peripheral USB device is desired, the device should
be connected to the downstream port and pass enumeration.
9.5 HC’s operational model
Upon power up, the HCD sets up all operational registers (32-bit). The
FSLargestDataPacket eld (bits 30 to 16) of the HcFmInterval register (0DH - Read,
8DH - Write) and the HcLSThreshold register (11H - Read, 91H - Write) determine
Table 6:
Run results of the C program example
Observed items
HC not initialized and not
under Operational state
HC initialized and under
Operational state
Comments
Hc
PInterrupt register
Bit 1 (ATLInt)
0
1
microprocessor must read ATL
Bit 2 (AllEOTInterrupt)
1
transfer completed
HcBufferStatus register
Bit 2 (ATLBufferFull)
1
transfer completed
Bit 5 (ATLBufferDone)
0
1
PTD data processed by HC
USB trafc on USB Bus
no
yes
OUT packets can be seen
Fig 20. PIO access to internal FIFO buffer RAM.
MGT951
Commands
Pointer
automatically
increments by 2
TransferCounter
BufferStatus
internal EOT
ITLBufferPort
ATLBufferPort
ATL buffer RAM
(8-bit width)
Control registers
Command register
data port
T
EOT
1
2
=
0
toggle
command port
PInterrupt
22H/A2H
2CH
40H/C0H
41H/C1H
24H/A4H
000H
7FFH
001H
ITL1 buffer RAM
(8-bit width)
000H
3FFH
001H
ITL0 buffer RAM
(8-bit width)
000H
3FFH
001H
A0
Host bus I/F
1
0
(16-bit width)
SOF
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