參數(shù)資料
型號： 935270538118
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 45/93頁
文件大?。?/td> 2118K
代理商： 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
5 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
D5
5
I/O
bit 5 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D6
6
I/O
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D7
7
I/O
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
8
-
digital ground
D8
9
I/O
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D9
10
I/O
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D10
11
I/O
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D11
12
I/O
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D12
13
I/O
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D13
14
I/O
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
15
-
digital ground
D14
16
I/O
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D15
17
I/O
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
18
-
digital ground
Vhold1
19
-
voltage holding pin 1; this pin is internally connected to the
Vreg(3.3) and Vhold2 pins. When pin VCC is connected to 5 V,
this pin will output 3.3 V and therefore, it must not be
connected to 5 V. When pin VCC is connected to 3.3 V, this
pin can either be connected to 3.3 V or left unconnected. In
all cases, this pin must be decoupled to DGND.
n.c.
20
-
not connected; leave this pin open
CS
21
I
chip select input
RD
22
I
read strobe input
WR
23
I
write strobe input
Vhold2
24
-
voltage holding pin 2; this pin is internally connected to the
Vreg(3.3) and Vhold1 pins. When pin VCC is connected to 5 V,
this pin will output 3.3 V and therefore, it must not be
connected to 5 V. When pin VCC is connected to 3.3 V, this
pin can either be connected to 3.3 V or left unconnected. In
all cases, this pin must be decoupled to DGND.
DREQ
25
O
HC’s DMA request output (programmable polarity); signals
to the DMA controller that the ISP1160 wants to start a
DMA transfer; see Section 10.4.1
n.c.
26
-
not connected; leave this pin open
Table 2:
Pin description for LQFP64…continued
Symbol[1]
Pin
Type
Description
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