- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24833 > 935270538118 (NXP SEMICONDUCTORS) UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 22/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
29 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
the end of the frame for full-speed and low-speed packets. By programming these
elds, the effective USB bus usage can be changed. Furthermore, the size of the ITL
buffers (HcITLBufferLength, 2AH - Read, AAH - Write) is programmed.
If a USB frame contains both ISO and AT packets, two interrupts will be generated
per frame.
One interrupt is issued concurrently with the SOF. This interrupt (ITLint is set in the
Hc
PInterrupt register) triggers reading and writing of the ITL by the microprocessor,
after which the interrupt is cleared by the microprocessor.
Next the programmable AT Interrupt (ATLint is set in the Hc
PInterrupt register) is
issued, which triggers reading and writing of the ITL by the microprocessor, after
which the interrupt is cleared by the microprocessor. If the microprocessor cannot
handle the ISO interrupt before the next ISO interrupt, disrupted ISO trafc can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, an active bit and a ’TotalBytes of transfer’ eld are introduced (see
Table 5). The active bit is cleared only if all data of the Philips Transfer Descriptor
(PTD) are transferred or if a transaction at that endpoint contained a fatal error. If all
PTD of the ATL are serviced once and the frame is not over yet, the HC starts looking
for a PTD with the active bit still set. If such a PTD is found and there is still enough
time in this frame, another transaction is started on the USB bus for this endpoint.
For ISO processing, the Host Controller Driver has also to take care of the
BufferStatus register (2CH, Read only) for the ITL buffer RAM operations. After the
Host Controller Driver writes ISO data into ITL buffer RAM, the ITL0BufferFull or
ITL1BufferFull bit (depends if it is ITL0 or ITL1) will be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM, the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.
The Host Controller Driver can clear buffer status bits by a read of the ITL buffer
RAM, and this must be done within the 1 ms frame from which ITL0BufferDone or
ITL1BufferDone was set. Failure to do so will cause the ISO processing to stop and a
power on reset or software reset will have to be applied to the HC, a USB reset to the
USB bus must not be made.
For example, in the rst frame, for the HCD doing a write of ISO-A data into the ITL0
buffer. This will cause the BufferStatus register to show that the ITL0 buffer is full by
setting the ITL0BufferFull bit to logic 1. At this stage the Host Controller Driver cannot
write ISO data into the ITL0 buffer RAM again.
In the second frame, the Host Controller will process the ISO-A data in the ITL0
buffer. At the same time, the HCD can write ISO-B data into the ITL1 buffer. When the
next SOF comes (the beginning of the third frame), both ITL1BufferFull and
ITL0BufferDone are automatically set to logic 1. In the third frame the HCD has to
read ITL0 buffer at least two bytes (one word) to clear both the ITL0BufferFull and
ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the
beginning of the fourth frame) the ITL0BufferDone bit will be cleared automatically,
but the ITL0BufferFull bit remains at logic 1 and the ITL0BufferFull bit will be unable
to be cleared. This condition will disable the HCD from writing ISO data into the ITL0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935270523557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 935270668112 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 935272535118 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 935272535157 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 935268661112 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
| 935270792551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270792557 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270793551 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
| 935270793557 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。