參數(shù)資料
型號(hào)： 935270538118
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 31/93頁(yè)
文件大?。?/td> 2118K
代理商： 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
37 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10. HC registers
The HC contains a set of on-chip control registers. These registers can be read or
written by the Host Controller Driver (HCD). The Control and Status register sets,
Frame Counter register sets, and Root Hub register sets are grouped under the
category of HC Operational registers (32 bits). These operational registers are made
compatible to OpenHCI (Host Controller Interface) operational registers. This makes
a provision that the OpenHCI HCD can be ported to the ISP1160 easily.
Reserved bits may be dened in future releases of this specication. To ensure
interoperability, the HCD that does not use a reserved eld must not assume that the
reserved eld contains logic 0. Furthermore, the HCD must always preserve the
values of the reserved eld. When a R/W register is modied, the HCD must rst read
the register, modify the bits desired, and then write the register with the reserved bits
still containing the read value. Alternatively, the HCD can maintain an in-memory
copy of previously written values that can be modied and then written to the
HC register. When a write to set or clear the register is written, bits written to reserved
elds must be logic 0.
As shown in Table 7, the offset locations (the commands for reading registers) of
these operational registers (the 32-bit registers) are similar to those dened in the
OHCI specication, however, the addresses are equal to offset divided by 4.
Table 7:
HC registers summary
Address (Hex)
Register
Width Functionality
Read
Write
00
N/A
HcRevision
32
HC control and status registers
01
81
HcControl
32
02
82
HcCommandStatus
32
03
83
HcInterruptStatus
32
04
84
HcInterruptEnable
32
05
85
HcInterruptDisable
32
0D
8D
HcFmInterval
32
HC frame counter registers
0E
N/A
HcFmRemaining
32
0F
N/A
HcFmNumber
32
11
91
HcLSThreshold
32
12
92
HcRhDescriptorA
32
HC Root Hub registers
13
93
HcRhDescriptorB
32
14
94
HcRhStatus
32
15
95
HcRhPortStatus[1]
32
16
96
HcRhPortStatus[2]
32
20
A0
HcHardwareConguration
16
HC DMA and interrupt control
registers
21
A1
HcDMAConguration
16
22
A2
HcTransferCounter
16
24
A4
Hc
PInterrupt
16
25
A5
Hc
PInterruptEnable
16
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