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參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 48/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
52 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 13 — read
Code (Hex): 93 — write
10.3.3
HcRhStatus register (14H—Read, 94H—Write)
The HcRhStatus register is divided into two parts. The lower word of a Dword
represents the Hub Status eld and the upper word represents the Hub Status
Change eld. Reserved bits should always be written as logic 0.
Table 31:
HcRhDescriptorB register: bit description
Bit
Symbol
Description
31 to 19
-
reserved
18 to 16
PPCM[2:0]
PortPowerControlMask: Each bit indicates whether a port is
affected by a global power control command when
PowerSwitchingMode is set. When set, the port’s power state is
only affected by per-port power control (Set/ClearPortPower).
When cleared, the port is controlled by the global power switch
(Set/ClearGlobalPower). If the device is congured to global
switching mode (PowerSwitchingMode = 0), this eld is not valid.
Bit 0 — reserved
Bit 1 — Ganged-power mask on Port #1
Bit 2 — Ganged-power mask on Port #2
15 to 3
-
reserved
2 to 0
DR[2:0]
DeviceRemovable: Each bit is dedicated to a port of the Root
Hub. When cleared, the attached device is removable. When set,
the attached device is not removable.
Bit 0 — reserved
Bit 1 — Device attached to Port #1
Bit 2 — Device attached to Port #2
Table 32:
HcRhStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
CRWE
reserved
Reset
00000000
Access
W
RRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
CCIC
LPSC
Reset
00000000
Access
RRRRRR
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
DRWE
reserved
Reset
00000000
Access
R/W
RRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
OCI
LPS
Reset
00000000
Access
RRRRRRR
R/W
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