參數(shù)資料
型號(hào)： 935270538118
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 39/93頁
文件大?。?/td> 2118K
代理商： 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
44 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 04 — read
Code (Hex): 84 — write
10.1.6
HcInterruptDisable register (05H—Read, 85H—Write)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
2SF
0 — ignore
1 — enable interrupt generation due to Start of frame
1
-
reserved
0SO
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
Table 17:
HcInterruptEnable register: bit description…continued
Bit
Symbol
Description
Table 18:
HcInterruptDisable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
reserved
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
00000000
Access
R/W
Table 19:
HcInterruptDisable register: bit description
Bit
Symbol
Description
31
MIE
A logic 0 is ignored by the HC. A logic 1 disables interrupt
generation due to events specied in other bits of this register. This
eld is set after a hardware or software reset.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — disable interrupt generation due to Root Hub Status Change
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