- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24833 > 935270538118 (NXP SEMICONDUCTORS) UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 40/93頁(yè) |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
45 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 05 — read
Code (Hex): 85 — write
10.2 HC frame counter registers
10.2.1
HcFmInterval register (0DH—Read, 8DH—Write)
The HcFmInterval register contains a 14-bit value which indicates the bit time interval
in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the
full-speed maximum packet size that the HC may transmit or receive without causing
a scheduling overrun. The HCD may carry out minor adjustments on the
FrameInterval by writing a new value over the present one at each SOF. This provides
the programmability necessary for the HC to synchronize with an external clocking
resource and to adjust any unknown local clock offset.
5
FNO
0 — ignore
1 — disable interrupt generation due to frame Number Overow
4UE
0 — ignore
1 — disable interrupt generation due to Unrecoverable Error
3RD
0 — ignore
1 — disable interrupt generation due to Resume Detect
2SF
0 — ignore
1 — disable interrupt generation due to Start of frame
1
-
reserved
0SO
0 — ignore
1 — disable interrupt generation due to Scheduling Overrun
Table 19:
HcInterruptDisable register: bit description…continued
Bit
Symbol
Description
Table 20:
HcFmInterval register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FIT
FSMPS[14:8]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
FSMPS[7:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FI[13:8]
Reset
00101110
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FI[7:0]
Reset
11011111
Access
R/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935270523557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 935270668112 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 935272535118 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 935272535157 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 935268661112 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
| 935270792551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270792557 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270793551 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
| 935270793557 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。