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參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 25/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
31 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.5.2
Control transaction limitations
The different phases of a Control transfer (SETUP, Data and Status) should never be
put in the same ATL.
9.6 Microprocessor loading
The maximum amount of data that can be transferred for an endpoint in one frame is
1023 bytes. The number of USB packets that are needed for this batch of data
depends on the Maximum Packet Size that is specied.
The HCD has to schedule the transactions in a frame. On the other hand, the
microprocessor must have the ability to handle the interrupts coming from the HC
every 1 ms. It must also be able to do the scheduling for the next frame, reading the
frame information from and writing the next frame information to the buffer RAM in the
time between the end of the current frame and the start of the next frame.
9.7 Internal pull-down resistors for downstream ports
There are four internal 15 k
pull-down resistors built in the ISP1160 for the two
downstream ports: two resistors for each port. These resistors are software
selectable by programming bit 12 of the HcHardwareConguration register
(20H - Read, A0H - Write). When bit 12 is cleared to logic 0, it means that external
15 k
pull-down resistors should be used. Bit 12 is set to logic 1 that indicates the
internal built in 15 k
pull-down resistors will be used instead of external ones. See
This feature is a cost-saving option. However, the power-on reset default value is
logic 0. If you want to use the internal resistors, the HCD must check this bit status
after every reset, because a reset action will clear this bit regardless of it being a
hardware reset or a software reset.
Fig 23. HC time domain behavior: example 3.
MGT956
(frame N)
(frame N
+ 1)
(frame N
+ 2)
(frame N
+ 3)
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