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參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 58/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
61 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10.4.4
Hc
PInterrupt register (24H—Read, A4H—Write)
All the bits in this register will be active on power-on reset. However, none of the
active bits will cause an interrupt on the interrupt pin (INT) unless they are set by the
respective bits in the Hc
PInterruptEnable register, and together with bit 0 of the
HcHardwareConguration register.
After this register (24H - Read) is read, the bits that are active will not be reset, until
logic 1 is written to the bits in this register (A4H - Write) to clear it.
The bits in this register are cleared only when you write to this register indicating the
bits to be cleared. To clear all the enabled bits in this register, the HCD must write
FFH to this register.
Table 42:
Hc
PInterrupt register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ClkReady
HC
Suspended
OPR_Reg
reserved
AIIEOT
Interrupt
ATLInt
SOFITLInt
Reset
00000000
Access
R/W
Table 43:
Hc
PInterrupt register: bit description
Bit
Symbol
Description
15 to 7
-
reserved
6
ClkReady
0 — no event
1 — clock is ready. After a wake-up is sent, there is a wait for clock
ready. Maximum is 1 ms, and typical is 160
s.
5HC
Suspended
0 — no event
1 — the HC has been suspended and no USB activity is sent from
the microprocessor for each ms. When the microprocessor wants
to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
4
OPR_Reg
0 — no event
1 — there are interrupts from HC side. Need to read HcControl
and HcInterrupt registers to detect type of interrupt on the HC (if
the HC requires the operational register to be updated).
3
-
reserved
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