參數(shù)資料
型號(hào): 935270538118
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 29/93頁
文件大?。?/td> 2118K
代理商: 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
35 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.9 Suspend and wake-up
9.9.1
HC suspended state
The HC can be put into suspended state by setting the HcControl register
(01H - Read, 81H - Write). See Figure 14 for the HC’s ow of USB states changes.
Fig 27. Using external OC detection circuit.
Vo
Vi
OC
EN
VCC
H_OCn
H_PSWn
H_DMn
H_DPn
USB
downstream
port
connector
47 pF
(2
×)
22
22
VBUS
+3.3 V or +5 V
+5 V
external
OC detect
004aaa067
ATX
1
0
Reg
PSW
OC select
OC detect
regulator
HC CORE
C/L
SIE
15 k
(2
×)
ISP1160
bit 10
bit 12
HcHardware
Configuration
HcHardware
Configuration
Fig 28. The ISP1160 suspend and resume clock scheme.
004aaa076
On
XOSC_6MHz
XOSC
On
VOLTAGE
REGULATOR
HC PLL
HC_ClkOk
HC_RawClk48M
HC_EnableClock
H_Wakeup (pin)
CS (pin)
HC_NeedClock
PLL_Lock
PLL_ClkOut
On
DIGITAL
CLOCK
SWITCH
HC
CORE
HC_Clk48MOut
HcHardware Configuration
bit 11 (SuspendClkNotStop)
相關(guān)PDF資料
PDF描述
935270523557 UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
935270668112 POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
935272535118 POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56
935272535157 POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56
935268661112 POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
935270713557 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP
935270792551 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
935270792557 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
935270793551 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA
935270793557 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA