- 您現(xiàn)在的位置：買賣IC網 > PDF目錄24833 > 935270538118 (NXP SEMICONDUCTORS) UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 PDF資料下載
參數資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 36/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
41 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 02 — read
Code (Hex): 82 — write
10.1.4
HcInterruptStatus register (03H—Read, 83H—Write)
This register provides the status of the events that cause hardware interrupts. When
an event occurs, the HC sets the corresponding bit in this register. When a bit
becomes set, a hardware interrupt is generated if the interrupt is enabled in the
HcInterruptEnable register (see Section 10.1.5) and the MasterInterruptEnable bit is
set. The HCD can clear specic bits in this register by writing logic 1 to the bit
positions to be cleared, but cannot set any of these bits. The HC can set bits in this
register, but cannot clear these bits.
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
HCR
Reset
00000000
Access
R/W
Table 13:
HcCommandStatus register: bit description
Bit
Symbol
Description
31 to 18
-
reserved
17 to 16
SOC[1:0]
SchedulingOverrunCount: The eld is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It will be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by HCD to monitor any persistent
scheduling problems.
15 to 1
-
reserved
0
HCR
HostControllerReset: This bit is set by HCD to initiate a software
reset of HC. Regardless of the functional state of the HC, it moves
to the USBSUSPEND state in which most of the operational
registers are reset except those stated otherwise; e.g., the
InterruptRouting eld of HcControl, and no Host bus accesses are
allowed. This bit is cleared by the HC upon the completion of the
reset operation. The reset operation must be completed within
10 s. This bit, when set, should not cause a reset to the Root Hub
and no subsequent reset signaling should be asserted to its
downstream ports.
Table 14:
HcInteruptStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
R/W
相關PDF資料 |
PDF描述 |
|---|---|
| 935270523557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 935270668112 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 935272535118 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 935272535157 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 935268661112 | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
| 935270792551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270792557 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270793551 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
| 935270793557 | 制造商:NXP Semiconductors 功能描述:IC BUS TRCVR 3-ST 16BIT 56VFBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復。