參數(shù)資料
型號(hào)： 935270538118
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 18/93頁
文件大?。?/td> 2118K
代理商： 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
25 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.4.3
Operation & C Program Example
Figure 20 shows the block diagram for internal FIFO buffer RAM operations by the
PIO mode. The ISP1160 provides one register as the access port for each buffer
RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register
(40H - Read, C0H - Write). For the ATL buffer RAM, the access port is the
ATLBufferPort register (41H - Read, C1H - Write). The buffer RAM is an array of
bytes (8 bits) while the access port is a 16-bit register. Therefore, each read/write
operation on the port accesses two consecutive memory locations, incrementing the
pointer of the internal buffer RAM by two.
The lower byte of the access port register corresponds to the data byte at the even
location of the buffer RAM, and the higher byte in the access port register
corresponds to the other data byte at the odd location of the buffer RAM. Regardless
of the number of data bytes to be transferred, the command code must be issued
merely once, and it will be followed by a number of accesses of the data port (see
When the pointer of the buffer RAM reaches the value of the HcTransferCounter
register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the
Hc
PInterrupt register and update the HcBufferStatus register, to indicate that the
whole data transfer has been completed.
For ITL buffer RAM, every start of frame (SOF) signal (1 ms) will cause toggling
between ITL0 and ITL1 but this depends on the buffer status. If both ITL0BufferFull
and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that
both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the
microprocessor will always have access to ITL1.
Fig 19. PTD data with DWORD alignment in buffer RAM.
MGT953
payload data
(14 bytes)
PTD
(8 bytes)
PTD
(8 bytes)
00H
top
08H
15H
18H
20H
payload data
RAM buffer
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