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參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 41/93頁 |
| 文件大小： | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
46 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 0D — read
Code (Hex): 8D — write
10.2.2
HcFmRemaining register (0EH—Read only)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame.
Table 21:
HcFmInterval register: bit description
Bit
Symbol
Description
31
FIT
FrameIntervalToggle: The HCD toggles this bit whenever it loads
a new value to FrameInterval.
30 to 16
FSMPS
[14:0]
FSLargestDataPacket: Species a value which is loaded into the
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits which
can be sent or received by the HC in a single transaction at any
given time without causing a scheduling overrun. The eld value is
calculated by the HCD.
15 to 14
-
reserved
13 to 0
FI[13:0]
FrameInterval: Species the interval between two consecutive
SOFs in bit times. The nominal value is set to be 11999. The HCD
must store the current value of this eld before resetting the HC.
By setting the HostControllerReset bit 0 eld of
HcCommandStatus register will cause the HC to reset this eld to
its nominal value. HCD may choose to restore the stored value
upon completing the reset sequence.
Table 22:
HcFmRemaining register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FRT
reserved
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FR[13:8]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
FR[7:0]
Reset
00000000
Access
RRRRRRRR
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