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參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 38/93頁 |
| 文件大小： | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
43 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
The MasterInterruptEnable bit is set.
Then a hardware interrupt is requested on the host bus.
Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Table 16:
HcInterruptEnable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
reserved
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
00000000
Access
R/W
Table 17:
HcInterruptEnable register: bit description
Bit
Symbol
Description
31
MIE
MasterInterruptEnable by the HCD: A logic 0 is ignored by
the HC. A logic 1 enables interrupt generation by events specied
in other bits of this register.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
5
FNO
0 — ignore
1 — enable interrupt generation due to frame Number Overow
4UE
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
3RD
0 — ignore
1 — enable interrupt generation due to Resume Detect
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