參數(shù)資料
型號: 935270538118
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 35/93頁
文件大?。?/td> 2118K
代理商: 935270538118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
40 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 01 — read
Code (Hex): 81 — write
10.1.3
HcCommandStatus register (02H—Read, 82H—Write)
The HcCommandStatus register is used by the HC to receive commands issued by
the HCD, and it also reects the HC’s current status. To the HCD, it appears to be a
‘write to set’ register. The HC must ensure that bits written as logic 1 become set in
the register while bits written as logic 0 remain unchanged in the register. The HCD
may issue multiple distinct commands to the HC without concern for corrupting
previously issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount eld indicates the number of frames with which the HC
has detected the scheduling overrun error. This occurs when the Periodic list does
not complete before EOF. When a scheduling overrun error is detected, the
HC increments the counter and sets the SchedulingOverrun eld in the
HcInterruptStatus register.
8
-
reserved
7 to 6
HCFS
HostControllerFunctionalState for USB:
00B — USBRESET
01B — USBRESUME
10B — USBOPERATIONAL
11B — USBSUSPEND
A transition to USBOPERATIONAL from another state causes
start-of-frame (SOF) generation to begin 1 ms later. The HCD may
determine whether the HC has begun sending SOFs by reading
the StartofFrame eld of HcInterruptStatus.
This eld may be changed by the HC only when in the
USBSUSPEND state. The HC may move from the USBSUSPEND
state to the USBRESUME state after detecting the resume
signaling from a downstream port.
The HC enters USBRESET after a software reset and a hardware
reset. The latter also resets the Root Hub and asserts subsequent
reset signaling to downstream ports.
5 to 0
-
reserved
Table 11:
HcControl register: bit description…continued
Bit
Symbol
Description
Table 12:
HcCommandStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
SOC[1:0]
Reset
00000000
Access
RRRRRRRR
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