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參數(shù)資料
| 型號： | 935270538118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 56/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270538118 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
6 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DACK
27
I
HC’s DMA acknowledge input; when not in use, this pin
must be connected to VCC via an external 10 k resistor
TEST_HIGH
28
-
this pin must be connected to VCC
INT
29
O
HC’s interrupt output; programmable level, edge triggered
and polarity; see Section 10.4.1
n.c.
30
-
not connected; leave this pin open
n.c.
31
O
not connected; leave this pin open
RESET
32
I
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset (internal pull-up resistor)
NDP_SEL
33
I
number of downstream ports:
0 — select 1 downstream port
1 — select 2 downstream ports
only changes the value of the NDP eld in the
HcRhDescriptorA register; both ports will always be
enabled (internal pull-up resistor)
EOT
34
I
DMA master device to inform the ISP1160 of end of DMA
transfer; active level is programmable; when not in use, this
pin must be connected to VCC via an external 10 k
resistor; see Section 10.4.1
DGND
35
-
digital ground
n.c.
36
-
not connected; leave this pin open
TEST_LOW
37
-
this pin must be connected to DGND
n.c.
38
O
not connected; leave this pin open
TEST_LOW
39
-
this pin must be connected to DGND
H_WAKEUP
40
I
HC’s wake-up input; generates a remote wake-up from
‘suspend’ state (active HIGH); when not in use, this pin
must be connected to DGND via an external 10 k
resistor
(internal pull-up resistor)
n.c.
41
-
not connected; leave this pin open
H_SUSPEND
42
O
HC’s suspend state indicator output; active HIGH
XTAL1
43
I
crystal input; connected directly to a 6 MHz crystal; when it
is connected to an external clock oscillator, leave
pin XTAL2 open
XTAL2
44
O
crystal output; connected directly to a 6 MHz crystal; when
pin XTAL1 is connected to an external clock oscillator,
leave this pin open
DGND
45
-
digital ground
H_PSW1
46
O
power switching control output for downstream port 1;
open-drain output
H_PSW2
47
O
power switching control output for downstream port 2;
open-drain output
TEST_LOW
48
-
this pin must be connected to DGND via an external
100 k
resistor
TEST_LOW
49
-
this pin must be connected to DGND via an external
100 k
resistor
Table 2:
Pin description for LQFP64…continued
Symbol[1]
Pin
Type
Description
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