
Operating Modes and On-Chip Memory
Memory Map
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Operating Modes and On-Chip Memory
79
$1038
Reserved
R
R
R
R
R
R
R
R
$1039
SystemConfiguration Options
Register (OPTION)
See page 91.
Read:
ADPU
CSEL
IRQE
(1)
DLY
(1)
CME
CR1
(1)
CR0
(1)
Write:
Reset:
0
0
0
1
0
0
0
0
$103A
Arm/Reset COP Timer
Circuitry Register (COPRST)
See page 111.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
$103B
EPROMand EEPROM
Programmng Control Register
(PPROG)
See page 95.
Read:
ODD
EVEN
ELAT
(2)
BYTE
ROW
ERASE
EELAT
EPGM
Write:
Reset:
0
0
0
0
0
0
0
0
$103C
Highest Priority I Bit Interrupt
and Mscellaneous Register
(HPRIO)
See page 83.
Read:
RBOOT
SMOD
MDA
IRV(NE)
PSEL3
PSEL2
PSEL1
PSEL0
Write:
Reset:
0
0
0
0
0
1
1
0
$103D
RAMand I/O Mapping
Register (INIT)
See page 89.
Read:
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
Write:
Reset:
0
0
0
0
0
0
0
1
$103E
Reserved
R
R
R
R
R
R
R
R
$103F
SystemConfiguration Register
(CONFIG)
See page 87.
Read:
NOSEC
NOCOP
ROMON
EEON
Write:
Reset:
0
0
0
0
U
U
1
U
$103F
SystemConfiguration Register
(CONFIG)
(3)
See page 87.
Read:
EE3
EE2
EE1
EE0
NOSEC
NOCOP
EEON
Write:
Reset:
1
1
1
1
U
U
1
1
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.
2. MC68HC711E9 only
3. MC68HC811E2 only
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
I = Indetermnate after reset
Figure 4-7. Register and Control Bit Assignments (Sheet 8 of 8)