
Electrical Characteristics
Peripheral Port Timing
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Electrical Characteristics
235
11.12 Peripheral Port Timing
Characteristic
(1)
(2)
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, all timing is shown with respect to 20% V
DD
and 70% V
DD
, unless
otherwise noted
2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers,
respectively.)
3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more
cycle.
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of operation
E-clock frequency
f
o
dc
1.0
dc
2.0
dc
3.0
MHz
E-clock period
t
cyc
1000
—
500
—
333
—
ns
Peripheral data setup time
MCU read of ports A, C, D, and E
t
PDSU
100
—
100
—
100
—
ns
Peripheral data hold time
MCU read of ports A, C, D, and E
t
PDH
50
—
50
—
50
—
ns
Delay time, peripheral data write
t
PWD
= 1/4 t
cyc
+ 100 ns
MCU writes to port A
MCU writes to ports B, C, and D
t
PWD
—
—
200
350
—
—
200
225
—
—
200
183
ns
Port C input data setup time
t
IS
60
—
60
—
60
—
ns
Port C input data hold time
t
IH
100
—
100
—
100
—
ns
Delay time, E fall to STRB
t
DEB
= 1/4 t
cyc
+ 100 ns
t
DEB
—
350
—
225
—
183
ns
Setup time, STRA asserted to E fall
(3)
t
AES
0
—
0
—
0
—
ns
Delay time, STRA asserted to port C data
output valid
t
PCD
—
100
—
100
—
100
ns
Hold time, STRA negated to port C data
t
PCH
10
—
10
—
10
—
ns
3-state hold time
t
PCZ
—
150
—
150
—
150
ns