
Technical Data
MC68HC11E Family
—
Rev. 4
112
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Special considerations are needed when a STOP instruction is executed
and the clock monitor is enabled. Because the STOP function causes
the clocks to be halted, the clock monitor function generates a reset
sequence if it is enabled at the time the stop mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register
to 0 to disable the clock monitor. After recovery from STOP, set the CME
bit to logic 1 to enable the clock monitor. Alternatively, executing a STOP
instruction with the CME bit set to logic 1 can be used as a software
initiated reset.
5.3.5 System Configuration Options Register
ADPU
—
Analog-to-Digital Converter Power-Up Bit
Refer to
Section 10. Analog-to-Digital (A/D) Converter
.
CSEL
—
Clock Select Bit
Refer to
Section 10. Analog-to-Digital (A/D) Converter
.
IRQE
—
Configure IRQ for Edge-Sensitive-Only Operation Bit
0 = IRQ is configured for level-sensitive operation.
1 = IRQ is configured for edge-sensitive-only operation.
DLY
—
Enable Oscillator Startup Delay Bit
Refer to
Section 4. Operating Modes and On-Chip Memory
and
Section 10. Analog-to-Digital (A/D) Converter
.
Address:
$1039
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADPU
CSEL
IRQE
(1)
DLY
(1)
CME
CR1
(1)
CR0
(1)
Write:
Reset:
0
0
0
1
0
0
0
0
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
= Unimplemented
Figure 5-2. System Configuration Options Register (OPTION)