
Technical Data
MC68HC11E Family
—
Rev. 4
74
Operating Modes and On-Chip Memory
MOTOROLA
Operating Modes and On-Chip Memory
$100C
Output Compare 1 Mask
Register (OC1M)
See page 191.
Read:
OC1M7 OC1M6
OC1M5
OC1M4
OC1M3
Write:
Reset:
0
0
0
0
0
0
0
0
$100D
Output Compare 1 Data
Register (OC1D)
See page 192.
Read:
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
Write:
Reset:
0
0
0
0
0
0
0
0
$100E
Timer Counter Register High
(TCNTH)
See page 193.
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
0
0
0
0
0
0
0
0
$100F
Timer Counter Register Low
(TCNTL)
See page 193.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
$1010
Timer Input Capture 1 Register
High (TIC1H)
See page 184.
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indetermnate after reset
$1011
Timer Input Capture 1 Register
Low (TIC1L)
See page 184.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indetermnate after reset
$1012
Timer Input Capture 2 Register
High (TIC2H)
See page 185.
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indetermnate after reset
$1013
TImer Input Capture 2
Register Low (TIC2L)
See page 185.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indetermnate after reset
$1014
Timer Input Capture 3 Register
High (TIC3H)
See page 185.
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indetermnate after reset
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
I = Indetermnate after reset
Figure 4-7. Register and Control Bit Assignments (Sheet 3 of 8)