
Technical Data
MC68HC11E Family
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Rev. 4
54
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
A 4-page opcode map has been implemented to expand the number of
instructions. An additional byte, called a prebyte, directs the processor
from page 0 of the opcode map to one of the other three pages. As its
name implies, the additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero,
one, two, or three operands. The operands contain information the CPU
needs for executing the instruction. Complete instructions can be from
one to five bytes long.
3.6 Addressing Modes
Six addressing modes can be used to access memory:
Immediate
Direct
Extended
Indexed
Inherent
Relative
These modes are detailed in the following paragraphs. All modes except
inherent mode use an effective address. The effective address is the
memory address from which the argument is fetched or stored or the
address from which execution is to proceed. The effective address can
be specified within an instruction, or it can be calculated.
3.6.1 Immediate
In the immediate addressing mode, an argument is contained in the
byte(s) immediately following the opcode. The number of bytes following
the opcode matches the size of the register or memory location being
operated on. There are 2-, 3-, and 4- (if prebyte is required) byte
immediate instructions. The effective address is the address of the byte
following the instruction.