
Technical Data
MC68HC11E Family
—
Rev. 4
76
Operating Modes and On-Chip Memory
MOTOROLA
Operating Modes and On-Chip Memory
$101E
Timer Input Capture 4/Output
Compare 5 Register High
(TI4/O5)
See page 186.
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
1
1
1
1
1
1
1
1
$101F
Timer Input Capture 4/Output
Compare 5 Register Low
(TI4/O5)
See page 186.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
1
1
1
1
1
1
1
1
$1020
Timer Control Register 1
(TCTL1)
See page 194.
Read:
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
Write:
Reset:
0
0
0
0
0
0
0
0
$1021
Timer Control Register 2
(TCTL2)
See page 183.
Read:
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
Write:
Reset:
0
0
0
0
0
0
0
0
$1022
Timer Interrupt Mask 1
Register (TMSK1)
See page 195.
Read:
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
Write:
Reset:
0
0
0
0
0
0
0
0
$1023
Timer Interrupt Flag 1
(TFLG1)
See page 196.
Read:
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
Write:
Reset:
0
0
0
0
0
0
0
0
$1024
Timer Interrupt Mask 2
Register (TMSK2)
See page 196.
Read:
TOI
RTII
PAOVI
PAII
PR1
PR0
Write:
Reset:
0
0
0
0
0
0
0
0
$1025
Timer Interrupt Flag 2
(TFLG2)
See page 201.
Read:
TOF
RTIF
PAOVF
PAIF
Write:
Reset:
0
0
0
0
0
0
0
0
$1026
Pulse Accumulator Control
Register (PACTL)
See page 202.
Read:
DDRA7
PAEN
PAMOD
PEDGE
DDRA3
I4/O5
RTR1
RTR0
Write:
Reset:
0
0
0
0
0
0
0
0
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
R
= Reserved
U = Unaffected
I = Indetermnate after reset
Figure 4-7. Register and Control Bit Assignments (Sheet 5 of 8)