參數(shù)資料
型號： 28F640C3
廠商： Intel Corp.
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導(dǎo)塊閃速存儲器)
中文描述： 3伏高級啟動塊閃存（3伏高級快速引導(dǎo)塊閃速存儲器）
文件頁數(shù)： 24/70頁
文件大小： 894K
代理商： 28F640C3
28F800C3, 28F160C3, 28F320C3, 28F640C3
18
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NOTES:
1. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ
, and Z = DQ
0
.
The current locking state of a block is defined by the state of WP# and the two bits of the block lock status
(DQ
, DQ
). DQ
indicates if a block is locked (1) or unlocked (0). DQ
1
indicates if a block has been locked-
down (1) or not (0).
2. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the
recommended default.
3.
The “Erase/Program Allowed” column shows whether erase and program operations are enabled (Yes) or
disabled (No) in that block’s current locking state.
4. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking
commands (Lock, Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would mean
that writing the command to a block in the current locking state would change it to [001].
3.4
128-Bit Protection Register
The 3 Volt Advanced+ Boot Block architecture includes a 128-bit protection register than can be
used to increase the security of a system design. For example, the number contained in the
protection register can be used to “mate” the flash component with other system components such
as the CPU or ASIC, preventing device substitution. Additional application information can be
found in Intel application note
AP-657
Designing with the Advanced+ Boot Block Flash Memory
Architecture
.
The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other
segment is left blank for customer designs to program as desired. Once the customer segment is
programmed, it can be locked to prevent reprogramming.
3.4.1
Reading the Protection Register
The protection register is read in the configuration read mode. The device is switched to this mode
by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses
shown in
Appendix G
retrieve the specified information. To return to read array mode, write the
Read Array command (FFH).
Table 9. Block Locking State Transitions
Current State
Erase/Prog
Allowed
Lock Command Input Result (Next State)
X
Y
Z
Lock
Unlock
Lock-Down
WP#
DQ
1
DQ
0
Name
0
0
0
“Unlocked”
Yes
Goes To [001]
No Change
Goes To [011]
0
0
1
“Locked” (Default)
No
No Change
Goes To [000]
Goes To [011]
0
1
1
“Locked-Down”
No
No Change
No Change
No Change
1
0
0
“Unlocked”
Yes
Goes To [101]
No Change
Goes To [111]
1
0
1
“Locked”
No
No Change
Goes To [100]
Goes To [111]
1
1
0
Lock-Down Disabled
Yes
Goes To [111]
No Change
Goes To [111]
1
1
1
Lock-Down Disabled
No
No Change
Goes To [110]
No Change
相關(guān)PDF資料
PDF描述
28F640J3C-120 Intel StrataFlash Memory (J3)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F640C3BC80 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3C120 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3C-120 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3D75 制造商:Intel 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J5 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory
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