參數(shù)資料
型號： 28F640C3
廠商： Intel Corp.
英文描述： 3 Volt Advanced Boot Block Flash Memory(3 V 高級快速引導塊閃速存儲器)
中文描述： 3伏高級啟動塊閃存（3伏高級快速引導塊閃速存儲器）
文件頁數(shù)： 12/70頁
文件大小： 894K
代理商： 28F640C3
28F800C3, 28F160C3, 28F320C3, 28F640C3
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Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS:
Memory addresses are internally latched during a program or erase cycle.
8-Mbit: A[0-18], 16-Mbit: A[0-19], 32-Mbit: A[0-20], 64-Mbit: A[0-21]
DQ
0
–DQ
7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle during a Program
command. Inputs commands to the Command User Interface when CE# and WE# are active.
Data is internally latched. Outputs array, configuration and status register data. The data pins float
to tri-state when the chip is de-selected or the outputs are disabled.
DQ
8
–DQ
15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle during a Program
command. Data is internally latched. Outputs array and configuration data. The data pins float to
tri-state when the chip is de-selected.
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers, decoders and sense amplifiers.
CE# is active low. CE# high de-selects the memory device and reduces power consumption to
standby levels.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers during a read
operation. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the command register and memory array. WE# is active low.
Addresses and data are latched on the rising edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to control reset/deep power-
down mode.
When RP# is at logic low, the device is in reset/deep power-down mode
, which drives the
outputs to High-Z, resets the Write State Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation
. When RP# transitions from
logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT:
Controls the lock-down function of the flexible Locking feature.
When WP# is a logic low, the lock-down mechanism is enabled
and blocks marked lock-down
cannot be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled
and blocks previously locked-
down are now locked and can be unlocked and locked through software. After WP# goes low, any
blocks previously marked lock-down revert to that state.
See
Section 3.3
for details on block locking.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
[2.7 V–3.6 V] Supplies power for device operations.
V
CCQ
INPUT
I/O POWER SUPPLY:
Supplies power for input/output buffers.
[2.7 V–3.6 V] This input should be tied directly to V
CC
.
V
PP
INPUT/
SUPPLY
PROGRAM/ERASE POWER SUPPLY:
[1.65 V–3.6 V or 11.4 V–12.6 V] Operates as a input at
logic levels to control complete device protection. Supplies power for accelerated program and
erase operations in 12 V
±
5% range. This pin cannot be left floating.
Lower
V
PP
≤
V
PPLK
, to protect all contents against Program and Erase commands.
Set V
= V
for in-system read, program and erase operations
. In this configuration, V
PP
can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note that if
V
PP
is driven by a logic signal, V
IH =
1.65. That is, V
PP
must remain above 1.65 V to perform in-
system flash modifications.
Raise V
PP
to 12 V
±
5% for faster program and erase in a production environment. Applying 12 V
±
5% to V
PP
can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles
on the parameter blocks.
V
PP
may be connected to 12 V for a total of 80 hours maximum. See
Section 3.4
for details on V
PP
voltage configurations.
GND
SUPPLY
GROUND:
For all internal circuitry. All ground inputs
must
be connected.
NC
NO CONNECT:
Pin may be driven or left floating.
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