
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October 2000
28
Lucent Technologies Inc.
Overview
(continued)
STS-3/STM-1 Overhead Processing
Receive Direction
Terminating the transport overhead (TOH), the super mapper performs frame alignment (STS-3/STM-1 or STS-1),
B1 BIP-8 check, J0 monitoring, descrambling, F1 monitoring, B2 BIP-8 check, APS and K2 monitoring, AIS-L and
RDI-L detection, M1 REI-L detection, S1 sync status monitoring, and transport overhead access channel (RTOAC)
drop.
The states of the framer as well as all state changes are reported, and, if not masked, cause an interrupt.
The B1 and B2 parity check supports bit and block mode. The counters count up to one second worth of BIP
errors. They stay at their maximum value in case of overflow or rollover and should be read (and cleared) at least
once per second.
The J0 monitor supports non-framed, SONET-framed, and SDH-framed 16-byte sequences as well as single J0
byte monitoring modes.
APS monitoring is performed on K1[7:0] and K2[7:3]. The value is stored and changes are reported. Bits [2:0] of
the K2 byte are monitored independently.
Line AIS (AIS-L/MS-AIS) and remote defect indication (RDI-L/MS-RDI) are monitored separately and changes are
reported. This information is also sent to the protection device for ADM applications.
The M1 monitor operates either in bit or block mode and allows accessing of the remote error indication (REI-L/MS-
REI) errored bit count.
The S1 byte can be monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits 7 to 4).
Continuous N times detection counters are implemented for these monitoring functions. All automatic receive mon-
itoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a
polled mode.
The receive transport overhead access channel (RTOAC) provides access to all of the line section overhead bytes.
Even or odd parity is calculated over all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and
an 8 kHz sync pulse. Alternatively, only the data communication channels D1—D3 or D4—D12 may transmit a
serial 192 kbits/s or a 576 kbits/s data stream.
Transmit Direction
In the transmit direction, the super mapper performs transmit transport overhead access channel (TTOAC) inser-
tion, sync status byte (S1) insertion, M0/M1—REI-L insertion, K1 and K2 insertion, AIS-L insertion, B2 calculation
and insertion, F1 byte insertion, B1 generation and error insertion, scrambler, J0 insert control, and A2 error inser-
tion. All insert control functions that are inhibited will optionally insert either all zeros or all ones. The transmit
TTOAC allows the users to insert the following overhead bytes: E1, F1, D1—D3, D4—D12, S1, and E2. Even or
odd parity is checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or all-zeros
stuff value. The super mapper sources a clock and an 8 kHz sync pulse and receives the data at a data rate of
5.184 Mbits/s. Alternatively, only the data communication channels D1—D3 or D4—D12 may receive a serial 192
kbits/s or a 576 kbits/s data stream.
The insertion (overwrite of TTOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled.
Automatic insertion of M0/M1 may be inhibited. A protection switch selects the REI-L value for insertion to be taken
from the protection board rather than from the receive side.
The entire APS value or K2[2:0] can be inserted via microprocessor control. Automatic RDI insertion is supported
with individual inhibit for each contributor. A protection switch selects the RDI-L value for insertion to be taken from
the protection board rather than from the receive side.
B1 and B2 BIP-8 values are calculated and inserted. Both values can be inverted.