
Preliminary Data Sheet, Rev. 1
October 2000
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
121
Lucent Technologies Inc.
TMUX Functional Description
(continued)
Transmit Direction (Transmit path to SONET/SDH line)
(continued)
Table 35 describes the encoding of the path RDI defects.
Table 35. RDI-P Defects for Enhanced RDI-P Mode
The TMUX provides a protection switch mux for RDI-P insertion. The mux is controlled by TMUX_TPREIRDISEL
(Table 69). If TMUX_TPREIRDISEL = 1, then the RDI-P value for insertion is taken from the value on the protec-
tion board rather than from the receive side of the same TMUX.
REI-P: G1(7:4) Insert
Four bits of the G1 byte G1(7:4) are allocated for use as path remote error indication (REI). For STS-1 signals and
for STM-1 signals these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been
detected in error by the BIP-8 (B3) detector on the received signal.
The automatic insertion of path REI can be inhibited on an STS-1 basis by programming the corresponding regis-
ter bits TMUX_TPREIINS[1:3] (Table 77) to 1. For STM-1 mode, only TMUX_TPREIINS[1] is relevant. If the regis-
ter bit(s) TMUX_TPREIINS[1:3] are programmed to 1, then one error is inserted into the G1 byte for that particular
STS-1(s) each time the microprocessor interface block SMPR_BER_INSRT (Table 13) bit is asserted.
The TMUX provides a protection switch mux for REI-P insertion. The mux is controlled by TMUX_TPREIRDISEL
(Table 69). If TMUX_TPREIRDISEL = 1, then the REI-P value for insertion is taken from the value on the protection
board rather than from the receive side of the same TMUX.
F2 Byte Insert
When TMUX_THSF2INS
= 1 (Table 70), the value in TMUX_TF2INS[1—3][7:0] (Table 76) is inserted into the out-
going
signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_F2 = 1 (Table 80). If both
TMUX_THSF2INS and TMUX_TPOAC_F2 = 0, then the value inserted depends on the value of microprocessor
interface block SMPR_OH_DEFLT (Table 15) bit. If SMPR_OH_DEFLT
= 0, then all 0s are inserted. If
SMPR_OH_DEFLT = 1, then all 1s are inserted.
G1
Bit 2
0
Triggers
Bit 3
0
Bit 1
0
No defects
(nonenhanced RDI-P mode)
No defects
(enhanced RDI-P mode)
LCD-P, PLM-P
(LCD-P not supported in Super Mapper)
No defects
(nonenhanced RDI-P mode)
AIS-P, LOP-P
(nonenhanced RDI-P mode)
AIS-P, LOP-P
(enhanced RDI-P mode)
TIM-P, UNEQ-P
(enhanced RDI-P mode)
AIS-P, LOP-P
(nonenhanced RDI-P mode)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1