
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October 2000
132
Lucent Technologies Inc.
TMUX Functional Description
(continued)
TMUX Register Descriptions
(continued)
Table 45. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)
Address
Bit
Name
Function
Reset
Default
0
0x40007
15
TMUX_RSFB3D1
Receive Path Signal Fail BER Algorithm Delta.
This delta
bit indicates a change of state for the signal fail BER algo-
rithm state bit TMUX_RSFB31 (Table 54) at the path level for
port 1. Only port 1 information is valid in AU-4 mode and in
STS-1 mode. The mask bit is TMUX_RSFB3M1 (Table 49).
Receive Path Signal Degrade BER Algorithm Delta.
This
delta bit indicates a change of state for the signal fail BER
algorithm state bit TMUX_RSDB31 (Table 54) at the path
level for port 1. Only port 1 information is valid in AU-4 mode
and in STS-1 mode. The mask bit is TMUX_RSDB3M1
(Table 49).
Receive Path Unequipped Event.
This event bit indicates
that the current value of the received C2 (signal label) byte,
TMUX_C2MON1[7:0] (Table 66), has a value 0x00, indicat-
ing unequipped payload on port 1. Only port 1 information is
valid in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RUNEQPM1 (Table 49).
Receive Path Payload Label Mismatch Event.
This event
bit indicates that the current value of the received C2 (signal
label) byte, TMUX_C2MON1[7:0], differs from the expected
C2 value, TMUX_C2EXP1[7:0] (Table 62) for port 1. Only
port 1 information is valid in AU-4 mode and in STS-1 mode.
The mask bit is TMUX_RPLMPM1 (Table 49).
Receive N1 Monitor Delta.
This delta bit indicates a change
in state in TMUX_N1MON1[7:0] (Table 66). The N1 current
value is updated when a consecutive and consistent value is
detected in the incoming N1 byte for TMUX_CNTDN1[3:0]
(Table 61) frames on port 1. Only port 1 information is valid
in AU-4 mode and in STS-1 mode. The mask bit is
TMUX_RN1MONM1 (Table 49).
Receive K3 Monitor Delta.
This delta bit indicates a change
in state in TMUX_K3MON1[7:0] (Table 66), which is updated
when a consecutive and consistent value is detected in the
incoming K3 byte for TMUX_CNTDK3[3:0] (Table 61) frames
on port 1. Only port 1 information is valid in AU-4 mode and
in STS-1 mode. The mask bit is TMUX_RK3MONM1
(Table 49).
14
TMUX_RSDB3D1
0
13
TMUX_RUNEQPE1
0
12
TMUX_RPLMPE1
0
11
TMUX_RN1MOND1
0
10
TMUX_RK3MOND1
0