
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet, Rev. 1
October 2000
266
Lucent Technologies Inc.
VT/TU Mapper Functional Description
(continued)
VT/TU Mapper Transmit Path Requirements
(continued)
Overhead Byte Generation (V5, J2, Z6/N2, Z7/K4, and O bits).
This portion of the VTGEN logic block will gener-
ate and insert the V5, J2, Z6/N2, and Z7/K4 overhead bytes into the appropriate virtual tributary. O bits are only
accessible in the asynchronous and bit synchronous modes.
V5 Overhead Byte Format/Generation.
The V5 overhead byte will be mapped as defined in Table 151.
Table 151. V5 Overhead Byte Format
The following features are supported:
I
When operating in tributary loopback mode (bit VT_LB_SEL[1—28] = 1 (Table 198)), all bits are simply passed
through transparently.
I
When operating in UPSR mode VT_V5_INS[1—28] = 1(Table 199), only a new BIP-2 and signal label is gener-
ated and inserted while all other bits are programmed from the received LOPOH serial access channel storage.
BIP-2 will be automatically calculated and inserted. The signal label is determined based on bits
VT_TX_MAPTYPE[1—28][3:0] (Table 198) and automatically inserted.
I
AIS-V is forced by setting bit, VT_AIS_INS[1—28] (Table 198) to a 1. AIS-V consists of overwriting the entire VT,
including V1~4, with all 1s.
I
Bits VT_TX_MAPTYPE[1—28][3:0] may be programmed to insert an UNEQ-V signal label. See Table 154, VT
Signal Label Definition on page 268.
I
User-controlled bits VT_BIP2ERR_INS[1—28][1:0] (Table 199) will force BIP-2 errors for troubleshooting pur-
poses. See Table 152 below for error insertion modes.
Table 152. BIP-2 Error Insertion Modes
I
When operating in UPSR mode VT_V5_INS[1—28] = 1, REI-V is set to the value in the received LOPOH serial
access channel storage when enabled by bit, VT_REI_EN[1—28] =1 (Table 198). When operating in normal
mode VT_V5_INS[1—28] = 0, REI-V is set to 1 for any detected BIP-2 errors in the corresponding received VT
when enabled by bit, VT_REI_EN = 1. Otherwise, the REI-V bit is set to 0.
I
RFI-V is supported. Manual control of the RFI-V bit is enabled with bit VT_RFI_EN[1—28] = 1 (Table 198). The
RFI-V bit is programmed with the value of bit VT_RFI_INS[1—28] (Table 200). When VT_RFI_EN[1—28] = 0
and operating in UPSR mode VT_V5_INS[1—28] = 1, RFI-V is set to the value in the received LOPOH serial
access channel storage. Otherwise, RFI-V is automatically generated and inserted as defined in Table 153, RDI-
V, RFI-V, and REI-V Automatic Generation on page 267. When operating in byte synchronous mode, RFI-V is
also based on the incoming DS1 RAI from the framer.
Bit 1
Bit 2
Bit 3
REI-V
Bit 4
RFI-V
Bit 5
SIGNAL LABEL
Bit 6
Bit 7
Bit 8
RDI-V
BIP-2
VT_BIP2ERR_INS[1—28][1:0]
(Table 199)
00
01
10
Action
No BIP-2 errors inserted.
Insert continuous BIP-2 errors.
Insert BIP-2 errors based on microprocessor register bit
SMPR_BER_INSRT (Table 13).
No BIP-2 errors inserted.
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