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參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 75/116頁(yè) |
| 文件大小： | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
71
Application Briefs
(continued)
Available Tools for Evaluation of the T7256
(continued)
IMPORTANT NOTE:
In order to use the SPEC_V2 with your product, you must adhere to the following guidelines:
I
Make sure none of the signals in the Signal Name column of Table 34 are hardwired to V
CC
or GND (with the
exception of GND
D
). If you need to tie any of these signals high or low, do it through a 5.1 k
resistor.
I
Make sure that circuitry on your board that is driving any of the Signal Name signals can be disabled (3-stated,
open collector output driver turned off, or signal trace cut, if necessary) when using the SPEC_V2.
Table 34. SPEC_V2 Interface Connector Pinouts
*
If RESET is not connected, the T7237/56 will not be RESET when exiting mode 2 or 3. If this is the case, the UUT must be powered down to
get the SCNT1 out of test mode.
J1
Pin
#
Signal
Name
SPEC_V2
Input/
Output
X
—
X
—
O
I
I
I
O
I
—
T7237/
56 Pin #
Notes
1
2
3
4
5
6
7
8
9
10
11
GND
D
—
GND
D
—
SCK
CKOUT
INT
SDO
SDI
PS1E
—
16
—
10
—
15
17
11
14
12
9
—
—
Connects to V
DDD
when interfacing to SCNT1-RDB.
—
—
—
—
—
—
—
PS1E becomes an output from T7237/56 in test mode.
Connects to PS2E (T7237/56 pin #8) when interfacing to
SCNT1_RDB.
12
13
14
TDMDI
SYN8K
—
I
7
4
—
—
—
O
—
Connects to ILOSS (T7237/56 pin #6) when interfacing to SCNT1-
RDB.
Recommended but not mandatory.*
HIGHZ becomes an output from T7237/56 in test mode.
15
16
RESET
HIGHZ
O
I
43
44
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