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參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 66/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
62
Lucent Technologies Inc.
Application Briefs
(continued)
Interfacing the T7256 to the Motorola
68302
Introduction
The Motorola MC68302 integrated multiprotocol pro-
cessor (IMP) contains a 68000 core integrated with a
flexible communications architecture. It has three serial
communications controllers (SCCs) that can be inde-
pendently programmed to support the following proto-
cols and physical interfaces.
Table 31. Motorola MC68302 SCC Options
The PCM interface option of the SCCs is appropriate
for interfacing to the T7256 TDM highway to provide
access to B- and D-channel data. The SCCs allow
ISDN B-channel transfers that support applications
such as V.120 rate adaption (synchronous HDLC
mode) and voice storage (transparent mode). However,
the T7256 does not output all signals that are required
to connect directly to the SCC and some external cir-
cuitry (e.g., an EPLD) is required in order to interface
the T7256 TDM highway to the MC68302 SCC PCM
highway. Users of the Motorola MC68360 should note
that the T7256 can be connected directly to the PCM
highway of the MC68360 without the use of any such
glue logic.
The MC68302 contains a 3-wire serial interface called
an SCP (serial communications port). The SCP may be
directly connected to the T7256 serial microprocessor
interface to control the T7256 register configuration.
The MC68302 also has programmable ports A (16 bits)
and B (12 bits) that are bit-wise programmable and can
be used as an alternative to the SCP to drive the T7256
serial microprocessor interface.
Figure 23 illustrates the interface connections between
the MC68302 and the T7256. A discussion of the TDM
and microprocessor interfaces follows.
Protocols
HDLC/SDLC
UART
BISYNC
DDCMP
Physical Interfaces
Motorola IDL
GCI
PCM Highway
NMSI (nonmultiplexed
serial interface)
—
—
V.110 Rate Adaption
Transparent
5-4046(C).b
Figure 23. MC68302 to T7256 Interface Diagram
MC68302
L1SY0
L1SY1
L1CLK
L1RXD
L1TXD
SPRXD
SPTXD
SPCLK
PB0
PB1
PB2
PARALLEL PORT B
SIGNALS
SCP
SIGNALS
PCM MODE
SIGNALS
– OR –
GLUE
LOGIC
T7256
FS
TDMCLK
TDMDO
TDMDI
SDO
SDI
SCK
SDO
SDI
SCK
MICROPROCESSOR
INTERFACE
(OPTION #2)
MICROPROCESSOR
INTERFACE
(OPTION #1)
TDM
INTERFACE
CKOUT
PA0
PA1
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