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參數(shù)資料
| 型號： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 52/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
48
Lucent Technologies Inc.
eoc State Machine Description
The following list shows the eight eoc states defined in
ANSI T1.601 and ETSI ETR 080. The bit pattern below
represents the state of U-interface overhead bits
eoci1—eoci8, respectively (see Table 2).
01010000—Operate 2B+D loopback.
01010001—Operate B1 channel loopback.
01010010—Operate B2 channel loopback.
01010011—Request corrupt CRC.
01010100—Notify of corrupted CRC.
11111111—Return to normal (default).
00000000—Hold state.
10101010—Unable to comply.
Normally, the T7256 automatically handles the eoc
channel processing per the ANSI and ETSI standards.
There may be some applications where manual control
of the eoc channel is desired (e.g., equipment that is
meant to test the eoc processing of upstream elements
by writing incorrect or delayed eoc data). This can be
accomplished by setting AUTOEOC = 0 (register GR0,
bit 4). The eoc state change interrupt is enabled by set-
ting EOCSCM = 0 (register UIR1, bit 0). This allows
state changes in the received eoc messages (registers
ECR2 and ECR3) to be indicated to the microproces-
sor by the assertion of UINT = 1 (register GIR0, bit 0)
and EOCSC = 1 (register UIR0, bit 0). The micropro-
cessor reads registers ECR2 and ECR3 to determine
which received eoc bits changed. Then, it updates the
transmit eoc values by writing registers ECR0 and
ECR1 and takes appropriate action (e.g., enable a
requested loopback). The total manual eoc procedure
consists of the following steps:
1. Microprocessor detects INT pin going low.
2. Microprocessor reads GIR0 and determines that
the UINT bit is set.
3. Microprocessor reads UIR0 and determines that the
EOCSC bit is set.
4. Microprocessor reads ECR2.
5. Microprocessor reads ECR3.
6. Microprocessor interprets newly received eoc mes-
sage and determines the appropriate response.
7. Microprocessor writes ECR0 based on results of
step 6.
8. Microprocessor writes ECR1 based on results of
step 6.
The maximum time allowed from the assertion of the
INT pin (step 1) until the completion of the last write
cycle to the eoc registers (step 8) is 1.5 ms.
ANSI Maintenance Control Description
The ANSI maintenance controller of the T7256 can
operate in fully automatic or in fully manual mode.
Automatic mode can be used in applications where
autonomous control of the metallic loop termination
(MLT) maintenance is desired. The MLT capability
implemented with the Lucent LH1465AB and an opto-
coupler provides a dc signature, sealing current sink,
and maintenance pulse-level translation for the testing
facilities. Maintenance pulses from the U-interface MLT
circuit are received by the OPTOIN pin and digitally fil-
tered for 20 ms. The device decodes these pulses
according to ANSI maintenance state machine require-
ments and responds to each request automatically.
For example, the T7256 will place itself in the quiet
mode if six pulses are received from the MLT circuitry.
Microprocessor interrupts in register MIR0 are avail-
able for tracking maintenance events if desired. Manual
mode can be used in applications where an external
maintenance decoder is used to drive the RESET and
ILOSS pins of the T7256. In this mode, the RESET pin
places the device in quiet mode and the ILOSS pin
controls SN1 tone transmission. Maintenance events
are not available in register MIR0 when in manual
mode.
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