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參數(shù)資料
| 型號： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 21/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
17
U-Interface Description
At the U-interface, the T7256 conforms to ANSI T1.601
and ETSI ETR 080 when used with the proper line
interface circuitry. The T7256 Reference Circuit
description in the Application Briefs section of this doc-
ument describes a detailed example of a U-interface
circuit design.
The 2B1Q line code provides a four-level (quaternary)
pulse amplitude modulation code with no redundancy.
Data is grouped into pairs of bits for conversion to qua-
ternary (quat) symbols. Figure 9 shows an example of
this coding method.
The U-interface transceiver section provides the 2B1Q
line coder (D/A conversion), pulse shaper, line driver,
first-order line balance network, clock regeneration,
and sigma-delta A/D conversion. The line driver, when
connected to the proper transformer and interface cir-
cuitry, generates pulses which meet the required 2B1Q
templates. The A/D converter is implemented by using
a double-loop, sigma-delta modulator.
The U transceiver block also takes input from the data
flow matrix and formats this information for the U-inter-
face (see Figure 1). During this formatting, synchroni-
zation bits for U framing are added and a scrambling
algorithm is applied. This data is then transferred to the
2B1Q encoder for transmission over the U-interface.
Signals received from the U-interface are first passed
through the sigma-delta A/D converter, and then sent
to the digital signal processor for more extensive signal
processing. The block provides decimation of the
sigma-delta output, linear and nonlinear echo cancella-
tion, automatic gain control, signal detection, phase
shift interpolation, decision feedback equalization, tim-
ing recovery, descrambling, and line-code polarity
detection. The decision feedback equalizer circuit pro-
vides the functionality necessary for proper operation
on subscriber loops with bridged taps.
A crystal oscillator provides the 15.36 MHz master
clock for the device. The on-chip, phase-locked loop
provides the ability to synchronize the chip to the line
rate.
The U-interface provides rapid cold start and warm
start operation. From a cold start, the device is typically
operational within four seconds. The interface supports
activation/deactivation, and when properly deactivated,
it stores the adaptive filter coefficients permitting a
warm start on the next activation request. A warm start
typically requires 200 ms for the device to become
operational.
5-2294 (C)
Figure 9. U-Interface Quat Example
–1
01
+3
10
+1
11
–3
00
–3
00
+1
11
+3
10
–3
00
–1
01
–1
01
+1
11
–1
01
–3
00
+3
10
+3
10
–1
01
+1
11
+3
+1
–1
–3
QUAT SYMBOL
BIT CODING
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