參數(shù)資料
型號(hào)： T7256A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁(yè)數(shù)： 7/116頁(yè)
文件大?。?/td> 1056K
代理商： T7256A
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
3
Table of Contents
(continued)
Figures
Page
Figure 1. Block Diagram......................................................................................................................................... 5
Figure 2. Pin Diagram............................................................................................................................................. 5
Figure 3. Applications of T7256............................................................................................................................ 10
Figure 4. U-Interface Frame and Superframe ...................................................................................................... 12
Figure 5. U-Interface Superframe Bit Groups....................................................................................................... 13
Figure 6. Frame Structures of NT and TE Frames............................................................................................... 14
Figure 7. Details of NT and TE Frames................................................................................................................ 15
Figure 8. Multiframing—S Subchannels and Q Subchannels .............................................................................. 16
Figure 9. U-Interface Quat Example..................................................................................................................... 17
Figure 10. S/T-Interface ASI Example.................................................................................................................. 18
Figure 11. Functional Register Map (Addresses and Bit Assignments)............................................................... 19
Figure 12.
NEC
and
Motorola
Microprocessor Port Connections......................................................................... 39
Figure 13.
Intel
Microprocessor Port Connections ............................................................................................... 39
Figure 14. Synchronous Microprocessor Port Interface Format........................................................................... 40
Figure 15. TDM Bus Time-Slot Format................................................................................................................. 42
Figure 16. B1-, B2-, D-Channel Routing............................................................................................................... 43
Figure 17. Location of the Loopback Configurations (Reference ITU-T I.430 Appendix I)................................... 44
Figure 18. STLED Control Flow Diagram............................................................................................................. 47
Figure 19. External Stimulus/Response Configuration......................................................................................... 51
Figure 20. T7256 Stand-Alone Reference Circuit-A............................................................................................. 54
Figure 21. T7256 Stand-Alone Reference Circuit-B............................................................................................. 55
Figure 22. T7256 NT1/TA Application Block Diagram.......................................................................................... 59
Figure 23. MC68302 to T7256 Interface Diagram................................................................................................ 62
Figure 24. SCNT1-RDB EPLD Schematic............................................................................................................ 64
Figure 25. SCNT1-RDB EPLD ADHL Design Files.............................................................................................. 65
Figure 26. SCNT1-RDB EPLD Timing (8-bit)....................................................................................................... 66
Figure 27. SCNT1-RDB EPLD Timing (7-bit)....................................................................................................... 67
Figure 28. TDM Bus Timing.................................................................................................................................. 76
Figure 29. Timing Diagram Referenced to SYN8K............................................................................................... 77
Figure 30. RESET Timing Diagram...................................................................................................................... 77
Figure 31. Switching Test Waveform.................................................................................................................... 78
Figure 32. Transceiver Impedance Limits ............................................................................................................ 82
Figure 33. Receiver Bias...................................................................................................................................... 90
Figure 34. T7256 S/T Line Interface Scheme....................................................................................................... 94
Figure 35. T7903 S/T Line Interface Scheme....................................................................................................... 94
Figure 36. T7250C S/T Line Interface Scheme.................................................................................................... 95
Figure 37. T7903 to T7256 Direct-Connect Scheme............................................................................................ 96
Figure 38. T7250C to T7256 Direct-Connect Scheme......................................................................................... 96
Figure 39. T7903 to T7256 Direct-Connect Scheme with External S/T-Interface ................................................ 97
Figure 40. T7250C to T7256 Direct-Connect Scheme with External S/T-Interface.............................................. 98
相關(guān)PDF資料
PDF描述
T7288 CEPT/E1 Line Interface(CEPT/E1 線接口)
T7290A DS1/T1/CEPT/E1 Line Interface(DS1/T1/CEPT/E1 線接口)
T7295-1 E3 Integrated Line Receiver(E3 集成線接收器)
T7295-6 DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器)
T7296 Integrated Line Transmitter(集成PCM線傳送器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T7257 制造商:TE Connectivity 功能描述:
T-726 制造商:RHOMBUS-IND 制造商全稱:Rhombus Industries Inc. 功能描述:ADSL Line Interface Transformers
T7263 制造商:TE Connectivity 功能描述:
T7263A 制造商:Toshiba America Electronic Components 功能描述:T7263A
T7264 制造商:TE Connectivity 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*