參數(shù)資料
型號： T7256A
英文描述： Compliance with the New ETSI PSD Requirement
中文描述： 符合新的ETSI PSD的要求
文件頁數(shù)： 13/116頁
文件大小： 1056K
代理商： T7256A
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
9
Pin Information
(continued)
Table 1. Pin Description
(continued)
* I
u
= input with internal pull-up; I
d
= input with internal pull-down.
Pin
25, 34,
40, 41
26
Symbol
GND
A
Type*
—
Name/Function
Analog Ground.
Ground leads for analog circuitry.
RNR
I
Receive Negative Rail for S/T-Interface.
Negative input of S/T-interface analog re-
ceiver. Connect to transformer through a 10 k
±
10% resistor.
Receive Positive Rail for S/T-Interface.
Positive input of S/T-interface analog re-
ceiver. Connect to transformer through a 10 k
±
10% resistor.
Common-Mode Voltage Reference for U-Interface Circuits.
Connect a
0.1
μ
F
±
20% capacitor to GND
A
(as close to the device pins as possible).
Positive Voltage Reference for U-Interface Circuits.
Connect a 0.1
μ
F
±
20% ca-
pacitor to GND
A
(as close to the device pins as possible).
Negative Voltage Reference for U-Interface Circuits.
Connect a 0.1
μ
F
±
20% ca-
pacitor to GND
A
(as close to the device pins as possible).
Hybrid Negative Input for U-Interface.
Connect directly to negative side of
U-interface transformer.
Line Driver Positive Output for U-Interface.
Connect to the U-interface transformer
through a 16.9
±
1% resistor.
Line Driver Negative Output for U-Interface.
Connect to the U-interface transform-
er through a 16.9
±
1% resistor.
Hybrid Positive Input for U-Interface.
Connect directly to positive side of
U-interface transformer.
Sigma-Delta A/D Negative Input for U-Interface.
Connect via an 820 pF
±
5%
capacitor to SDINP.
Sigma-Delta A/D Positive Input for U-Interface.
Connect via an 820 pF
±
5%
capacitor to SDINN.
Reset (Active-Low).
Asynchronous Schmitt trigger input. Reset halts data transmis-
sion, clears adaptive filter coefficients, resets the U-transceiver timing recovery cir-
cuitry, resets the S/T-interface transceiver, and sets all microprocessor register bits
to their default state. During reset, the U-interface transmitter produces 0 V and the
output impedance is 135
at tip and ring. The RESET pin can be used to implement
quiet mode maintenance testing (refer to pin 2 for more description). The states of
pins 11, 12, and 15 (ACTMODE/INT, SYN8K_CTL/SDI, and AUTOACT/SCK, respec-
tively) are latched on the rising edge of RESET. (See corresponding pin descriptions.)
An internal 100 k
pull-down resistor is on this pin. RESET must be held low for
1.5 ms after power on. Device is fully functional after an additional 1 ms.
High-Impedance Control (Active-Low).
Control of the high-impedance function. An
internal 100 k
pull-up resistor is on this pin.
Note:
This pin does not 3-state the an-
alog outputs.
0—All digital outputs enter high-impedance state.
1—No effect on device operation.
27
RPR
I
28
VRCM
—
29
VRP
—
30
VRN
—
31
HN
I
32
LOP
O
35
LON
O
36
HP
I
37
SDINN
I
38
SDINP
I
43
RESET
I
d
44
HIGHZ
I
u
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