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參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 65/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
61
Application Briefs
(continued)
D-Channel Priority
(continued)
Activation Control
Because there is no guarantee that a TE will be con-
nected in this application, the local microprocessor
must be provisioned to perform a layer-1 activation
request as follows:
1. Write AUTOACT = 0 (register GR0, bit 6) to initiate
start-up on the U-interface. This results in XACT = 1
(register CFR1, bit 1). The AUTOACT bit will be set
to a 1 automatically after the start-up request is
made. This permits another activation attempt by
writing AUTOACT = 0 again (without first writing it
back to 1) if the start-up attempt fails.
A switch-initiated start-up is detected by the local
microprocessor when XACT = 1 (register CFR1, bit
1). This event can be indicated by an interrupt (INT,
pin 11) by writing the interrupt mask bit OUSCM = 0
(register UIR1, bit 3) and calling the interrupt routine
when UINT = 1 (register GIR0, bit 0). The OUSC
interrupt (register UIR0, bit 3) indicates a bit change
in either CFR1 or CFR2. Read these registers to
determine which of these bits has changed since
the last read.
In either of the above cases, it may be necessary to
set the sai[1:0] bits in register GR1 to 01. This has
the effect of indicating S/T-interface activity to the
switch even when no TE is attached. Some switches
require the reception of sai = 1 in order to properly
establish layer 1 transparency.
2. Look for XACT = 0 or OOF = 1 (register CFR1, bits
1 and 2). These events can be indicated by an inter-
rupt INT, pin 11) in a similar manner as described in
(1) above.
3. If XACT = 0, the start-up attempt has failed and
appropriate action should be taken depending on
the system requirements (it may be desirable to
attempt another start-up).
4. If OOF = 1, U-interface synchronization is complete.
Set ACTT = 1 (register GR1, bit 4). This will set the
upstream ACT = 1 on the U-interface independent
of actions on the S/T-interface. It may be desirable
to delay several tens of milliseconds between
detecting OOF and setting ACTT = 1 to allow the
S/T-interface time to activate if there is a TE present.
If this is the case, the upstream act bit will automati-
cally be set, but manually setting ACTT = 1 is per-
missible.
5. After setting ACTT = 1, wait for ACTR = 1 (register
CFR1, bit 0). This event can be indicated by an
interrupt (INT, pin 11) in a similar manner as
described in (1) above. The reception of ACTR = 1,
enables U-interface transparency in the upstream
direction, so it is not necessary to do so explicitly by
setting XPCY = 0 (register GR1, bit 5).
At this point, layer-1 activation is complete. Note that
the above steps 1—5 occur automatically if there is a
TE connected or if the LT starts up and sends an eoc
loopback-2 request (2B+D loopback). However, having
the microprocessor perform these steps ensures layer
1 activation independently of the presence of a TE.
After layer 1 activation is complete, the XACT bit (regis-
ter CFR1, bit 1) can be monitored for a state change to
0. This provides an indication to the local microproces-
sor that layer 1 has deactivated. When this occurs, set
ACTT = 0 (register GR1, bit 4) to prepare for the next
start-up attempt.
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