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參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 54/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
50
Lucent Technologies Inc.
S/T-Interface Multiframing Controller
Description
(continued)
Once multiframing has been enabled, the microproces-
sor can read the Q-channel data that is received and
control the S subchannel data that is transmitted via
registers MCR0—MCR5. The reception of a new Q-
channel message is indicated to the microprocessor
when interrupt bit QSC = 1 (Q-Bits State Change bit,
register SIR0 bit 1). The microprocessor is informed
that a new S-subchannel message may be transmitted
when interrupt bit SOM = 1 (Start of Multiframe bit, reg-
ister SIR0, bit 0). To enable the SOM and QSC inter-
rupts, set SOMM = 0 and QSCM = 0 (register SIR1,
bits 0 and 1). When an interrupt occurs, the global
interrupt bits (register GIR0) can be read by the micro-
processor to determine the source of the interrupt (reg-
ister UINT, SINT, or MINT). An interrupt asserted in the
SIR0 register is indicated by SINT = 1. Reading the
SIR0 interrupt register clears the SOM and QSC inter-
rupt bits in preparation for the next occurrence. It
should be noted that the SOM interrupt is asserted
27
μ
s after the start of a multiframe and the S-subchan-
nel bits are latched in the MCR1—MCR5 registers
3
μ
s prior to the start of the next multiframe. Since
30
μ
s (27
μ
s + 3
μ
s) of time is used by the device, the
microprocessor has 4.97 ms of a total 5 ms multiframe
to load the next value of S-subchannel bits. The Q-
channel bits in the MCR0 register are updated every
multiframe at the same time that SOM is asserted.
Changes in any of the Q bits are indicated to the micro-
processor by QSC = 1.
Board-Level Testing
The T7256 provides several board-level testability fea-
tures. For example, the HIGHZ pin 3-states all digital
outputs for bed-of-nails testing. Also, various loopbacks
can be used to verify device functionality.
Stimulus/Response Testing
Data transparency of the B1, B2, and D channels can
be verified by the combined use of the TDM bus and
microprocessor port. Data flow within the device can be
configured by the external controller through the micro-
processor port, and B1-, B2-, and D-channel data can
be transmitted into and received from the device via the
TDM bus. Using this method, arbitrary data patterns
can be used to stimulate the device and combinations
of loopbacks can be exercised to help detect and iso-
late faults. Figure 19 illustrates this general-purpose
testing configuration.
TDMDI data can be routed through the device and
back to TDMDO at both the U- or S/T-interfaces. For
looping at U-interface, the procedure is as follows:
I
Disconnect the U-interface from the telephone net-
work.
I
Set TDMEN = 0 in register GR2, bit 5.
I
Set register DFR0 to 11110101.
I
Set register DFR1 to 00011110.
I
Set register TDR0 as required for the desired frame
strobe location and polarity.
Now, write LPBK in register GR1 to a 0. This causes
the chip to enter the U-interface loopback mode. Any
data entering the TDM highway on TDMDI will be
looped back (with some delay) on TDMDO.
For looping of the S/T-interface, the procedure is as fol-
lows:
I
Set TDMEN = 0 in register GR2, bit 5.
I
Set register DFR0 to 01011111.
I
Set register DFR1 to 11100001.
I
Set register TDR0 as required for the desired frame
strobe location and polarity.
I
Set AFRST = 0 (register CFR0, bit 1) and STOA = 0
(register GR2, bit 7). This causes the S/T-interface to
force activation while keeping the U-interface inac-
tive.
Now, externally short the transmit pins to the receive
pins on the S/T-interface (e.g., in Figure 21, short
J2—4 to J2—3 and short J2—5 to J2—6). This causes
a loopback of the S/T-interface that results in TDMDI
data being looped to TDMDO.
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