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參數(shù)資料
| 型號： | T7295-6 |
| 廠商： | Lineage Power |
| 英文描述： | DS3/SONET STS-1 Integrated Line Receiver(DS3/SONET STS-1 集成線接收器) |
| 中文描述： | DS3/SONET STS - 1的集成線路接收器（DS3/SONET STS - 1的集成線接收器） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 416K |
| 代理商： | T7295-6 |
Data Sheet
February 1997
T7295-6 DS3/SONET STS-1
Integrated Line Receiver
Features
I
Fully integrated receive interface supports
DS3 and STS-1 rate signals
both
I
Integrated equalization (optional) and timing
recovery
I
Loss-of-signal and loss-of-lock alarms
I
Variable input sensitivity control
I
5 V power supply
I
Intended for use in systems that must comply with
ITU-T G.703, ITU-T G.824, Bellcore TR-NWT-
000499, ANSI T1.104, and ANSI T1.102
I
Direct replacement for either the T7295-3 or
T7295-5 devices
Description
The T7295-6 DS3/SONET STS-1 Integrated Line
Receiver is a fully integrated receive interface that
terminates a bipolar DS3 (44.736 Mbits/s) or SONET
STS-1 (51.84 Mbits/s) signal transmitted over coaxial
cable. Another version of this device is available for
operation at the E3 (34.368 Mbits/s) data rate.
The device also provides the functions of receive
equalization (optional), automatic-gain control
(AGC), clock recovery and data retiming, and loss-of-
signal and loss-of-frequency-lock detection. The digi-
tal system interface is dual rail, with received positive
and negative 1s appearing as unipolar digital signals
on separate output leads. The on-chip equalizer is
designed for cable distances of 0 ft. to 450 ft. from
the cross connect frame to the device. High input
sensitivity allows for significant amounts of flat loss
within the system. An input reference clock provides
the frequency reference for the device to operate at
both the DS3 and SONET STS-1 rates. Figure 1
shows the block diagram of the device.
The T7295-6 device is manufactured using linear
CMOS technology and is packaged in a 20-pin, plas-
tic DIP or a 20-pin, plastic SOJ package for surface
mounting.
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